Deep sub-micron ESD GGNMOS layout design and optimization

Abstract

In the field of integrated circuits, ESD (Electro Static Discharge) has always been a rather serious problem of reliability. Enhanced ESD tolerance of IC chips became a focus of research on IC failure protection design. The thesis is better to solve the multi-fingered non-uniform conduction of ESD devices under electrostatic pulse. Layout parameters DCGS (Drain-Contact to Gate Spacing), SCGS (Source-Contact to Gate Spacing) and BS (Substrate-source spacing) size in the paper can be used as reference for ESD GGNMOS (Gated Ground NMOS) layout design. Also this paper provides setting the DRC (Design Rule Check) command to check the distance between the N+ diffusion regions of different potentials so that ESD failure is prevented effectively. TLP (Transmission Line Pulse) current pulse signal is adopted to measure characteristics of the GGNMOS. The thesis descripts a ESD Optimal layout design from five aspects of introduction, Key elements of ESD circuits layout design, ESD layout optimization, a ESD GGNMOS layout instance and conclusion.