Deep submicrometer SOI MOSFET drain current model including series resistance, self-heating and velocity overshoot effects

Roldán, J.B.; Gamiz, F.; López‐Villanueva, J. A.; Cartujo-Cassinello, P.

doi:10.1109/55.841308

Cited by 15 publications

(7 citation statements)

References 12 publications

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“…2(a) increased with the decrease of temperature when T > 300 K. As ambient temperature was increased, HCE degradation was suppressed due to the occurrence of phonon scattering, reducing channel electron mobility, and impact ionization rates. The self-heating effect of SoI device, which makes more phonons available for scattering, shortened the mean free path and affected ballistic transport characteristics of the carriers flight across the channel [17]. Thus, for FD SoI nMOSFETs at high temperature, HCE degradation decreased with the increase in temperature.…”

Section: A Low-temperature Operationmentioning

confidence: 99%

A Simulation Study of Hot Carrier Effects in SoI-Like Bulk Silicon nMOS Device

Wang

Shan

2015

IEEE Trans. Electron Devices

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A silicon-on-insulator (SoI)-like bulk silicon (SLBS) MOSFET structure is studied and compared against a fully depleted (FD) SoI MOSFET using 2-D numerical simulations. A p/n − /p + structure was contained in SLBS device, in which n − is made of 4H-SiC. This n − layer is FD. Hot carrier (HC) effects (HCEs) in proposed SLBS nMOSFET were simulated and compared with that in FD SoI nMOSFET. In this paper, HC-induced device degradation is characterized under different temperatures. HCE of SLBS always has an advantage over that of SoI. The worst case bias condition for HCEs has also been studied and was found as V gs = 1/2V ds . Index Terms-Bulk silicon, fully depleted (FD) siliconon-insulator (SoI) nMOS, hot carrier effects (HCEs), SoI-like.

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Section: A Low-temperature Operationmentioning

confidence: 99%

A Simulation Study of Hot Carrier Effects in SoI-Like Bulk Silicon nMOS Device

Wang

Shan

2015

IEEE Trans. Electron Devices

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“…From the modeling perspective, SHEs are taken into account following the approach described in [5]: the lattice temperature in channel is linearly related to the power dissipated in the device as,…”

Section: Thermal Modelmentioning

confidence: 99%

“…Once the general expression for the inversion charge is developed for all the operation regimes, the drain current (6) is calculated as in [6], where į o is a parameter introduced in [5] to account for velocity saturation effects. From (5), Q s = Q(V = 0) and Q d = Q(V = V ds ).…”

Section: Drain Current Modelmentioning

confidence: 99%

An advanced drain current model for DGMOSFETs including self-heating effects

González

Iñı́guez

Lázaro

et al. 2012

2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)

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An advanced drain current model for symmetrical Double-Gate MOSFETs (DGMOSFETs), including short channel, velocity saturation and self-heating effects, is presented. The temperature dependence of the low-field mobility, saturation velocity and inversion charge is analyzed and accurately included in the model. Self-heating is considered through the thermal resistance of the device, which is estimated in two ways: from an equivalent thermal circuit and from numerical output characteristic curves, obtained with a commercial TCAD tool (Sentaurus by Synopsys), and fitted with a drain current model. The validity of the model is checked by comparing with simulation results, for the typical bias range used in integrated circuits.

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“…It is noteworthy that SOI MOSFETs have many attractive advantages as compared to bulk silicon technology, such as lower power dissipation, higher speed, and extended scalability. [10][11][12][13] Moreover, SOI technology is also compatible with now available bulk silicon technology in terms of manufacturing. Nowadays, continuously reducing the channel length of the SOI MOSFET is an admirable endeavor aimed at benefiting from the improved electrical performance brought about by the downsizing.…”

Section: Introductionmentioning

confidence: 99%

Two-dimensional analytical model for a non-lightly doped drain SOI MOSFET

Xu,

Cui,

et al. 2024

Jpn. J. Appl. Phys.

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A two-dimensional (2D) analytical model considering the effects of the gate oxide region, channel region, and buried oxide region for a non-lightly doped drain (LDD) SOI MOSFET is proposed. The top and bottom surface potential distributions have been derived on the basis of solving 2D Poisson’s equation and using an evanescent mode analysis. The potential distribution, threshold voltage, and threshold voltage roll-off have been verified by Silvaco ATLAS simulated results for the proposed device with different device parameters. The model agrees well with the simulation results under the above-mentioned conditions. Therefore, the analytical model provides the basic designing guidance for non-LDD SOI MOSFETs.

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Deep submicrometer SOI MOSFET drain current model including series resistance, self-heating and velocity overshoot effects

Cited by 15 publications

References 12 publications

A Simulation Study of Hot Carrier Effects in SoI-Like Bulk Silicon nMOS Device

A Simulation Study of Hot Carrier Effects in SoI-Like Bulk Silicon nMOS Device

An advanced drain current model for DGMOSFETs including self-heating effects

Two-dimensional analytical model for a non-lightly doped drain SOI MOSFET

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