DeepHLS: A complete toolchain for automatic synthesis of deep neural networks to FPGA

Riazati, Mohammad; Daneshtalab, Masoud; Sjödin, Mikael; Lisper, Björn

doi:10.1109/icecs49266.2020.9294881

Cited by 9 publications

(4 citation statements)

References 14 publications

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“…The approach proposed in this paper goes beyond the state of the art by establishing a fully automated tool for enabling efficient AxC in FPGA-based DNN accelerators aimed at reliability-critical applications. The proposed Deep-Axe framework is integrated into DeepHLS environment [12], which is capable of providing completely synthesizable code for efficient FPGA implementations. In particular, this work extends DeepHLS with fault simulation, resiliency analysis and also the use of AxC.…”

Section: Related Workmentioning

confidence: 99%

“…High-Level Synthesis (HLS) tools bridge high-level programming and hardware implementation and allow overcoming the complexity of the process and reducing the design time. Recently, DNN-tailored HLS tools were proposed, e.g., CNN2gate [11], fpgaConvNet [11] and DeepHLS [12]. Such tools are capable of providing a synthesizable C implementation of DNNs for FPGAs from a high-level description in a language such as e.g., Keras.…”

Section: Introductionmentioning

confidence: 99%

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DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators

Taheri¹,

Riazati²,

Ahmadilivani³

et al. 2023

Preprint

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While the role of Deep Neural Networks (DNNs) in a wide range of safety-critical applications is expanding, emerging DNNs experience massive growth in terms of computation power. It raises the necessity of improving the reliability of DNN accelerators yet reducing the computational burden on the hardware platforms, i.e. reducing the energy consumption and execution time as well as increasing the efficiency of DNN accelerators. Therefore, the trade-off between hardware performance, i.e. area, power and delay, and the reliability of the DNN accelerator implementation becomes critical and requires tools for analysis.In this paper, we propose a framework DeepAxe for design space exploration for FPGA-based implementation of DNNs by considering the trilateral impact of applying functional approximation on accuracy, reliability and hardware performance. The framework enables selective approximation of reliability-critical DNNs, providing a set of Pareto-optimal DNN implementation design space points for the target resource utilization requirements. The design flow starts with a pre-trained network in Keras, uses an innovative high-level synthesis environment DeepHLS and results in a set of Pareto-optimal design space points as a guide for the designer. The framework is demonstrated on a case study of custom and state-of-the-art DNNs and datasets.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators

Taheri¹,

Riazati²,

Ahmadilivani³

et al. 2023

Preprint

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show abstract

“…Also, in [7] an open source tool which translates Tensorflow designs into Cloud FPGAs is described. A tool to translate high level Keras descriptions of DNNs into low level C code is shown in [8]. Finally, in [9] a Python package to create DNN implementations on low-cost FPGAs is developed.…”

Section: Introductionmentioning

confidence: 99%

A library-based tool to translate high level DNN models into hierarchical VHDL descriptions

Rubio‐Ibáñez

Martínez-Álvarez

Doménech‐Asensi

2021

2021 XXXVI Conference on Design of Circuits and Integrated Systems (DCIS)

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This work presents a tool to convert high level models of deep neural networks into register transfer level designs. In order to make it useful for different target technologies, the output designs are based on hierarchical VHDL descriptions, which are accepted as input files for a wide variety of FPGA, SoC and ASIC digital synthesis tools. The presented tool is aimed to speed up the design and synthesis cycle of such systems and provides the designer with certain capability to balance network latency and hardware resources. It also provides a clock domain crossing to interface the input layer of the synthesized neural networks with sensors running at different clock frequencies. The tool is tested with a neural network which combines convolutional and fully connected layers designed to perform traffic sign recognition tasks and synthesized under different hardware resource usage specifications on a Zynq Ultrascale+ MPSoC development board.

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“…Además, en [41] se describe una herramienta de código abierto que traduce diseños desarrollados mediante Tensorflow a FPGAs en la nube. En [42] se muestra una herramienta de traducción de descripciones de alto nivel en Keras de DNNs a código C de bajo nivel. Finalmente, en [43] se desarrolla un paquete para Python que permite crear implementaciones de DNNs para FPGAs de bajo coste.…”

Section: Módulos Para Dnnsunclassified

Design and synthesis methodology on reconfigurable hardware for real-time image processing architectures

Ibañez¹

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DeepHLS: A complete toolchain for automatic synthesis of deep neural networks to FPGA

Cited by 9 publications

References 14 publications

DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators

DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators

A library-based tool to translate high level DNN models into hierarchical VHDL descriptions

Design and synthesis methodology on reconfigurable hardware for real-time image processing architectures

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