DEFACTO: A design environment for adaptive computing technology

Abstract

The lack of high-level design tools hampers the widespread adoption of adaptive computing systems. Application developers have to master a wide range of functions, from the high-level architecture design, to the timing of actual control and data signals. These systems are extremely cumbersome and error-prone, making it difficult for adaptive computing to enter mainstream computing. In this paper we describe DEFACTO, an end-to-end design environment aimed at bridging the gap in tools for adaptive computing by bringing together parallelizing compiler technology and synthesis techniques. IntroductionAdaptive computing systems consisting of configurable computing logic can offer significant performance advantages over conventional processors as they can be tailored to the particular computational needs of a given application (e.g., template-based matching, Monte Carlo simulation, and string matching algorithms). Unfortunately, developing programs that incorporate configurable computing units (CCUs) is extremely cumbersome, demanding that software developers also assume the role of hardware designers. At present, developing applications on most such systems requires low-level VHDL coding, and complex management of communication and control. While a few application developers tools are being designed, these have been narrowly focused on a single application or a specific configurable architecture [1]. The absence of general-purpose, highlevel programming tools for adaptive computing applications has hampered the widespread adoption of this technology; currently, this area is only accessible to a very small collection of specially trained individuals. This paper describes DEFACTO, an end-to-end design environment for developing applications mapped to adaptive computing architectures. A user of DEFACTO develops an application in a high-level programming language such as C, possibly augmented by pragmas that specify variable arithmetic precision and timing requirements. The system maps this application to an adaptive computing architecture that consists of multiple FPGAs as coprocessors to a conventional general-purpose processor. Other inputs to the system include a description of the architecture (e.g., how many FPGAs, communication time and bandwidth), and applicationspecific information such as representative program inputs. DEFACTO leverages parallelizing compiler technology based on the Stanford SUIF compiler. While much existing compiler technology is directly applicable to this domain, adaptive computing environments present new challenges to a compiler, particularly the requirement of defining or selecting the functionality of the target architecture. Thus, a design environment for adaptive computing must also leverage CAD research to manage mapping configurable computations to actual hardware. DEFACTO combines compiler technology, CAD environments and techniques specially developed for adaptive computing in a single system. The remainder of the paper is organized into four sections and a conclusion. In ...

A Survey and Evaluation of FPGA High-Level Synthesis Tools

“…DEFACTO [39] is one of the early design environments that proposed hardware/software co-design solutions as an answer to increasing demands for computational power. DEFACTO is composed of a series of tools such as a profiler, partitioner and software and hardware compilers to perform fast design space exploration given a set of design constraints.…”

Increasing hardware efficiency with multifunction loop accelerators

“…One of the first efforts to automatically map applications onto an FPGA was Splash [7], subsequently productized as the NAPA system [8]. Other automatic compiler systems for FPGA-based platforms include GARP [2], PRISM [24], and DEFACTO [1]. Modulo scheduling has been used [19,12] to map critical loops onto reconfigurable coprocessors.…”

Techniques for synthesizing binaries to an advanced register/memory structure

“…In the first iteration, the smart buffer fetches the first four array elements that make up the first window. The window of the second iteration contains three elements (A [1], A [2], and A [3]) from the window of the first iteration. In this case, the smart buffer only fetches a single element (A [4]).…”

“…Many synthesis tools [1][7] use a control/data flow graph as input. The decompiler could therefore create a control/data flow graph for the software binary and annotate the control/data flow graph with high-level information denoting loops, arrays, etc.…”