Defect and Transient Fault-Tolerant System Design for Hybrid CMOS/Nanodevice Digital Memories

IET Comput. Digit. Tech.

2010

We propose two fault tolerance techniques for hybrid CMOS/nano architecture implementing logic functions as Look-Up Tables. We compare the efficiency of the proposed techniques with recently reported methods that use single coding schemes in tolerating high fault rates in nanoscale fabrics. Both proposed techniques are based on error correcting codes to tackle different fault rates. In the first technique, we implement a combined two dimensional coding scheme using Hamming and BCH codes to address fault rates greater than 5%. In the second technique, Hamming coding is complemented with Bad Line Exclusion technique to tolerate fault rates higher than the first proposed technique (up to 20%). We have also estimated the improvement that can be achieved in the circuit reliability in the presence of Don't Care Conditions. The area, latency and energy costs of the proposed techniques were also estimated in the CMOS domain.

“…The simplest form of BCH codes is the single error-correcting BCH (7,4,1) which is equivalent to Hamming code. We first examine BCH [13] with 0% Don't Care…”

Section: B Bose-chaudhuri-hocquenghem (Bch)mentioning

confidence: 99%

Section: B Hamming With Bad Line Exclusion : Techniquementioning

confidence: 99%

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Fault-tolerance techniques for hybrid CMOS/nanoarchitecture

IET Comput. Digit. Tech.

2010

“…The gain in device density that can be achieved using nanoscale devices presents a compelling case for developing hybrid nano/CMOS computing architecture [1], [2], [3], [4]. In a hybrid nano/CMOS architecture, unreliable but highly dense nano devices are used to provide data storage and computation while CMOS devices are utilized for interfacing and for highly critical circuit operations.…”

Section: Introductionmentioning

confidence: 99%

Tagged Repair Techniques for Defect Tolerance in Hybrid Nano/CMOS Architecture

IEEE Trans. Nanotechnology

2011

Abstract-We propose two new repair techniques for hybrid nano/CMOS computing architecture with lookup table based Boolean logic. Our proposed techniques use tagging mechanism to provide high level of defect tolerance and we present theoretical equations to predict the repair capability including an estimate of the repair cost. The repair techniques are efficient in utilization of spare units and capable of targeting upto 20% defect rates, which is higher than recently reported repair techniques.

“…Lithography-based technology used in current CMOS fabrication and bottom-up fabrication approach using self assembly has so far proven to be inadequate in building reliable nano circuits. However, the tremendous gain in device density that can be achieved using nanoscale systems presents a compelling case for developing hybrid nano/CMOS computing architecture [2], [3], [4] where unreliable but highly dense nano/molecular systems are used to provide data storage and computation while CMOS components are utilized for interfacing and for highly critical circuit operations. To achieve acceptable levels of defect tolerance for nano/CMOS architecture efficient repair techniques need to be implemented.…”

Section: Introductionmentioning

confidence: 99%

Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism

2009 IEEE/ACM International Symposium on Nanoscale Architectures

2009

Abstract-In this paper we propose two efficient repair techniques for hybrid nano/CMOS architecture to provide high level of defect tolerance at a modest cost. We have applied the proposed techniques to a lookup table(LUT) based Boolean logic approach. The proposed repair techniques are efficient in utilization of spare units and viable for various Boolean logic implementations. We show that the proposed techniques are capable of handling upto 20% defect ratess in hybrid nano/CMOS architecture and upto 14% defect rates for large ISCAS'85 benchmark circuits synthesized into smaller sized LUTs.