Defect-oriented vs schematic-level based fault simulation for mixed-signal ICs

A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis

“…Device fault modeling has proven to be a complex problem even under the assumption of wafer-level consideration. Two approaches are mainstream in device fault modeling [6], namely: i) Inductive Fault Analysis (IFA) [7], and ii) transistor level fault modeling [8].…”

“…For example, a missing spot is represented by a subcircuit of a high impedance resistor in parallel with a small capacitor. A low impedance resistor represents an extra spot that causes a short [6]. In the case of a Gate-Oxide short (GOS) with the channel, the n+ spot in the p-type channel is represented by a p-n diode.…”

“…This comprehensive set of defects is injected in each NMOS and PMOS transistor [6], [11] by creating a transistor macro replacement circuit. A total of 16 defects were considered for each transistor, roughly divided in 2 classes: hard and soft faults, concerning values used for resistors representing missing and unwanted spots.…”

Built-in-self-test of analogue circuits using optimised fault sets and transient response testing

“…Previously published studies using Inductive Fault Analysis (IFA) in order to predict the most likely faults in analogue circuits have generally deduced that short circuits are by far more common than open circuits [7,8]. We have similarly derived a reduced fault set by producing a typical circuit layout, shown in Figure 2, then running IFA (VLASIC [9]) using some process defect statistics provided by an industrial partner.…”

“…In order to define a fault detection we ran a Monte Carlo simulation of the fault-free circuit using industrial parameters and specified that for a fault to be classified as detectable, it must result in a response that is outside of the normal fault-free Monte Carlo spread. An open circuit was modelled using 100MΩ in parallel with a 1fF capacitor, since HSPICE does not permit floating nodes, and a short circuit by a 1Ω resistor [7,8]. Secondly we want to detect as many of the faults as possible, but need to quantify fault coverage in the light of the IFA results.…”