Defect tolerant probabilistic design paradigm for nanotechnologies

Abstract

Recent successes in the development and self-assembly of nanoelectronic devices suggest that the ability to manufacture dense nanofabrics is on the near horizon. However, the tremendous increase in device density of nanoelectronics will be accompanied by a substantial increase in hard and soft faults, posing a major challenge to current design methodologies and tools. In this paper we propose a novel probabilistic design paradigm for defective but reconfigurable nanofabrics. The new design goal is to devise an appropriate structural/behavioral decomposition which improves scalability by constraining the reconfiguration process, while meeting a desired probability of successful instantiation, i.e, yield. Our approach not only addresses the scalability problem in configuring dense nanofabrics subject to defects, but gives a rich framework in which critical tradeoffs among performance, yield, and per chip cost can be explored. We present a concrete instance of the approach and show extensive experimental results supporting these claims.

Advances in Nanowire-Based Computing Architectures

“…New research in multi-scale fault-tolerance and reliability techniques is, therefore, critically needed for commercial adoption of emergent nanotechnologies (Heath et al, 1998). It is anticipated that NRCA will have significantly higher defect density than CMOS, as high as 10% (Huang et al, 2004;Jacome et al, 2004). High-density fabrication could potentially be very inexpensive if researchers can actualize a chemical self-assembly, but such a circuit would require laborious testing, diagnosis, repair and reconfiguration processes, implying a significant overhead cost, as well.…”

Fault-tolerance techniques for hybrid CMOS/nanoarchitecture

“…BCH is a multilevel, variable length and easy to decode ECC used to correct multiple random errors in a codeword. The simplest form of BCH codes is the single error-correcting BCH (7,4,1) which is equivalent to Hamming code. We first examine BCH [13] with 0% Don't Care…”

“…The plots for simulation results of the circuit failure rate for Hamming (7,4,1), BCH (31,16,3) and 2D coding techniques are shown in Fig. 9.…”

Fault‐ and Defect‐Tolerant Architectures for Nanocomputing

“…Figure 10.4 shows a nanofabric composed of a grid of PEs connected together. This model is a combination of the nanofabric models used in [22] and [26]. The PEs are modeled to function as simple single-bit arithmetic logic units (ALUs), 8-bit adders or 8-bit combinational multipliers depending on the application being targeted.…”