2020
DOI: 10.1109/ted.2019.2959299
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Degradation Behavior and Mechanisms of E-Mode GaN HEMTs With p-GaN Gate Under Reverse Electrostatic Discharge Stress

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Cited by 35 publications
(8 citation statements)
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“…This pulsed negative V GS bias stress modulates the negatively charged trap density with an increase in V GS bias stress and increase in stress pulse (t stress ). However, the p-GaN gate HEMT device structure has no oxide layer compared with the MIS-HEMT device, which tells us that the reported surface state trapping mechanisms with oxide layer are not applicable here, although some research on the reliability of commercialized E-mode GaN HEMT with p-GaN gate under reverse electrostatic discharge stress and repetitive short circuit stress has reported that the degradation mechanism could be addressed by the formation of traps at the barrier layer, p-GaN/AlGaN hetero-interface, and AlGaN/GaN interface [26,27]. At the present work, we studied the degradation behavior and mechanism for the impact of various negative gate stress voltage pulses without drain stress bias at room temperature.…”
Section: Gate-lag Effectmentioning
confidence: 90%
“…This pulsed negative V GS bias stress modulates the negatively charged trap density with an increase in V GS bias stress and increase in stress pulse (t stress ). However, the p-GaN gate HEMT device structure has no oxide layer compared with the MIS-HEMT device, which tells us that the reported surface state trapping mechanisms with oxide layer are not applicable here, although some research on the reliability of commercialized E-mode GaN HEMT with p-GaN gate under reverse electrostatic discharge stress and repetitive short circuit stress has reported that the degradation mechanism could be addressed by the formation of traps at the barrier layer, p-GaN/AlGaN hetero-interface, and AlGaN/GaN interface [26,27]. At the present work, we studied the degradation behavior and mechanism for the impact of various negative gate stress voltage pulses without drain stress bias at room temperature.…”
Section: Gate-lag Effectmentioning
confidence: 90%
“…The degradation behavior under reverse electrostatic discharge stress (EDS) is analyzed using transmission line pulse (TLP) tester. 143,144 Moreover, the gate reliability issues arising at high temperature (>150 C) and high gate voltages are interpreted through the gate metal retraction (GMR) process. 145 On the other hand, the gate reliability enhancement of a p-GaN Gate HEMT is fulfilled using surface reinforcement.…”
Section: Reliabilitymentioning
confidence: 99%
“…However, owing to the lack of discharge path in the gate electrode of the p-GaN HEMTs, the devices exhibit poor ESD robustness in the gate-to-source condition, with an equivalent V HBM of only 0.2~0.33 kV. E. Canato [15] and Yiqiang Chen [16,17] reported the gate-tosource ESD failure and degradation mechanisms of p-GaN HEMTs, which mainly rely on the trapping effect and device geometry. To improve the gate-to-source ESD robustness for the p-GaN HEMT, Xin et al reported a unidirectional AlGaN/GaN ESD protection diode based on a self-triggered discharging channel [14].…”
Section: Introductionmentioning
confidence: 99%