Degradation of Rise Time in NAND Gates Using 2.0 nm Gate Dielectrics

Impact of single pMOSFET dielectric degradation on NAND circuit performance

“…It can be assumed R SD is small compared to R ch [25,26] and remains fairly constant after CVS, as the majority of the pMOSFET degradation occurs in the channel [21]. Therefore, equation (4) can be reduced to (9) or equivalently, (10) A correlation between %ΔR ch and g sdm can be derived from equation (10). ΔR ch can be written as (11) Using a common dominator, (11) can be written as (12) Dividing by R ch,Fresh to convert (12) to fractional percent change results in (13) Using equation (13), %ΔR ch was calculated using the small-signal conductance data.…”

“…This method has been used to investigate inverter logic circuit performance following degradation of a single MOSFET (or both MOSFETs) [4] in which degradation of MOSFET parameters was examined and directly correlated to inverter degradation in the voltage time-domain (V-t). The switch matrix technique has also been employed in a preliminary investigation on the degradation of rise time (t r ) in the NAND gate [9]. This study expands the preliminary investigation of NAND gate performance following pMOSFET degradation by comparing NAND circuit degradation in the DC and V-t domains.…”