Degradations due to hole trapping in flash memory cells

Haddad, S.; Chang, Chih‐Yung; Swaminathan, Balaji; Lien, Jih

doi:10.1109/55.31687

Cited by 71 publications

(24 citation statements)

References 9 publications

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“…3) Endurance: Cycling is known to cause a fairly uniform wear-out of cell performance [59], which eventually limits Flash memory endurance. A typical result of an endurance test on a single cell is shown in Fig.…”

Section: ) Programming Disturbsmentioning

confidence: 99%

Flash memory cells-an overview

et al. 1997

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Section: ) Programming Disturbsmentioning

confidence: 99%

Flash memory cells-an overview

et al. 1997

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“…Both exact a toll on the devices ability to be re-programmed by the degradation of the silicon through electron trapping in the oxide. As the electrons are punched through the insulating material some electrons get stuck, obstructing the path of subsequent electrons (Haddad et al 1989;Pavan et al 1997). The accumulated trapped charge in the oxide eventually makes the cell un-programmable, that is, the cell's state can no longer be altered.…”

Section: Flash Memory Operationmentioning

confidence: 98%

“…The purpose of Electrically Erasable Programmable Read Only Memory (EEPROM or E 2 PROM) is to retain settings after the power has been removed and to be electrically alterable in circuit when the power is applied. In recent times, floating gate memory devices such as flash memory have become the overwhelming technology of choice for those applications that require non-volatile semiconductor memory (Aritome et al 1993;Haddad et al 1989;IEEE Std 1998). There are three broad categories of EEPROM (Aritome et al 1993;IEEE Std 1998;Silicon Storage Technology, Inc. 1991):…”

Section: Flash Memorymentioning

confidence: 99%

A destructive evolutionary algorithm process

Sullivan

Ryan

2009

Soft Comput

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This paper describes the application of evolutionary search to the problem of flash memory wear-out. Flash memory differs from standard RAM in that it can wear out due to the manner in which it is programmed. The operating parameters, such as voltage levels, of flash memory are notoriously difficult to determine, as the optimal values vary from batch to batch. The current method in use is an expensive and time-consuming manual process of destructive testing. Understandably, this process is normally undertaken only at design time and testing on individual batches is normally not feasible. The results are sub-optimum solutions which do not minimise wear-out over the lifetime of the device. This is an enormously important issue in manufacturing, as most Flash Memory devices requiring reliability (e.g. solid state device disk drives) often have 100% or more redundancy to compensate for the wear-out rates. We establish the viability of a hardware platform that utilises an Evolutionary Algorithm to perform destructive experimentation on hard silicon in order to discover optimal or, at least favourable, operating parameter settings automatically in a manufacturing environment. Here, we describe this hardware and reveal results demonstrating an average life extension of between 250 and 350% over the factory set conditions with a maximum life extension exhibited of 700% all for cells within the same device over the factory settings. Furthermore, since the process is automated, it is possible to leverage the spread between process batches to further enhance device specifications, facilitating the near no-cost life extension of a split-gate flash memory device.

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“…This effect is particularly noticeable in infrequentlyprogrammed cells [24], which is likely the case for cells holding a secret key. Prior work has shown that this bias can survive even tens of redundant "clean-up" writes, making complete erasure of the information difficult within the time dictated by a countermeasure [17]. SRAM: Even volatile memories are subject to analysis in many cases.…”

Section: Physical Inspection Attacksmentioning

confidence: 99%

Inspection resistant memory: Architectural support for security from physical examination

Valamehr

Chase

Kamara

et al. 2012

2012 39th Annual International Symposium on Computer Architecture (ISCA)

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The ability to safely keep a secret in memory is central to the vast majority of security schemes, but storing and erasing these secrets is a difficult problem in the face of an attacker who can obtain unrestricted physical access to the underlying hardware. Depending on the memory technology, the very act of storing a 1 instead of a 0 can have physical side effects measurable even after the power has been cut. These effects cannot be hidden easily, and if the secret stored on chip is of sufficient value, an attacker may go to extraordinary means to learn even a few bits of that information. Solving this problem requires a new class of architectures that measurably increase the difficulty of physical analysis. In this paper we take a first step towards this goal by focusing on one of the backbones of any hardware system: on-chip memory. We examine the relationship between security, area, and efficiency in these architectures, and quantitatively examine the resulting systems through cryptographic analysis and microarchitectural impact. In the end, we are able to find an efficient scheme in which, even if an adversary is able to inspect the value of a stored bit with a probabilistic error of only 5%, our system will be able to prevent that adversary from learning any information about the original un-coded bits with 99.9999999999% probability.

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Degradations due to hole trapping in flash memory cells

Cited by 71 publications

References 9 publications

Flash memory cells-an overview

Flash memory cells-an overview

A destructive evolutionary algorithm process

Inspection resistant memory: Architectural support for security from physical examination

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