Delay-Bounded Routing for Shadow Registers

Abstract

The on-chip timing behaviour of synchronous circuits can be quantified at run-time by adding shadow registers, which allow designers to sample the most critical paths of a circuit at a different point in time than the user register would normally. In order to sample these paths precisely, the path skew between the user and the shadow register must be tightly controlled and consistent across all paths that are shadowed. Unlike a custom IC, FPGAs contain prefabricated resources from which composing an arbitrary routing delay is not trivial. This paper presents a method for inserting shadow registers with a minimum skew bound, whilst also reducing the maximum skew. To preserve circuit timing, we apply this to FPGA circuits post place-and-route, using only the spare resources left behind. We find that our techniques can achieve an average STA reported delay bound of ±200ps on a Xilinx device despite incomplete timing information, and achieve <1ps accuracy against our own delay model.

Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits

“…Zick et al propose using low-cost ring oscillators (ROs) that output to a residue number system [34]. Hung et al propose a time-to-digital converter that uses shadow registers to precisely measure individual wires and logic [14]. As discussed in the next section, we have decided to use counter-based ring oscillators to characterize the FPGA.…”