Delay Compression: Reducing Delay Calculation Requirements for 3D Plane-Wave Ultrasound

West, Brendan L.; Zhou, Jian; Chakrabarti, Chaitali; Wenisch, Thomas F.

doi:10.1109/ultsym.2019.8925725

Cited by 2 publications

(2 citation statements)

References 11 publications

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“…To improve the parallelization efficiency, we adopt the delay compression methods introduced in [22] and modify it for FPGA implementation.…”

Section: B Delay Profile Compression and Reusementioning

confidence: 99%

“…The other solution is to compress the delay profile to enable the precalculated delay profile loading at the run-time [18]. A delay compression technique that recognizes additional symmetry between the round-trip times for all focal points drastically reduces the delay profile size [22] and a low power 3D beamformer has been designed on an application-specific integrated circuit (ASIC) based on this method [19].…”

Section: Introductionmentioning

confidence: 99%

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High-Level Synthesis Design of Scalable Ultrafast Ultrasound Beamformer With Single FPGA

Kou

You

Kim

et al. 2023

IEEE Trans. Biomed. Circuits Syst.

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Ultrafast ultrasound imaging is essential for advanced ultrasound imaging techniques such as ultrasound localization microscopy (ULM) and functional ultrasound (fUS). Current ultrafast ultrasound imaging is challenged by the ultrahigh data bandwidth associated with the radio frequency (RF) signal, and by the latency of the computationally expensive beamforming process. As such, continuous ultrafast data acquisition and beamforming remain elusive with existing software beamformers based on CPUs or GPUs. To address these challenges, the proposed work introduces a novel method of implementing an ultrafast ultrasound beamformer specifically for ultrafast plane wave imaging (PWI) on a field programmable gate array (FPGA) by using high-level synthesis. A parallelized implementation of the beamformer on a single FPGA was proposed by 1) utilizing a delay compression technique to reduce the delay profile size, which enables both run-time pre-calculated delay profile loading from external memory and delay reuse 2) vectorizing channel data fetching which is enabled by delay reuse, and 3) using fixed summing networks to reduce consumption of logic resources. Our proposed method presents two unique advantages over current FPGA beamformers: 1) high scalability that allows fast adaptation to different FPGA resources and beamforming speed demands by using Xilinx High-Level Synthesis as the development tool, and 2) allow a compact form factor design by using a single FPGA to complete the beamforming instead of multiple FPGAs. Current Xilinx FPGA provides the capabilities of connecting up to 1024 ultrasound channels with a single FPGA and the newest JESD204B interface analog front end (AFE). This channel count is much more than the channel count needed by current linear arrays, which normally have 128 or 256 channels. With the proposed method, a sustainable average beamforming rate of 4.83 G samples/second in terms of input raw RF sample was achieved. The resulting image quality of the proposed beamformer was compared with the software beamformer on the Verasonics Vantage system for both phantom imaging and in vivo imaging of a mouse brain. Multiple imaging schemes including B-mode, power Doppler and ULM were assessed to verify that the image quality was not compromised for speed.

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“…To improve the parallelization efficiency, we adopt the delay compression methods introduced in [22] and modify it for FPGA implementation.…”

Section: B Delay Profile Compression and Reusementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

High-Level Synthesis Design of Scalable Ultrafast Ultrasound Beamformer With Single FPGA

Kou

You

Kim

et al. 2023

IEEE Trans. Biomed. Circuits Syst.

View full text Add to dashboard Cite

show abstract

A Reconfigurable Architecture of a Scalable, Ultrafast, Ultrasound, Delay-and-Sum Beamformer

Kypriotis,

Smaragdos,

Kruizinga

et al. 2024

2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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Delay Compression: Reducing Delay Calculation Requirements for 3D Plane-Wave Ultrasound

Cited by 2 publications

References 11 publications

High-Level Synthesis Design of Scalable Ultrafast Ultrasound Beamformer With Single FPGA

High-Level Synthesis Design of Scalable Ultrafast Ultrasound Beamformer With Single FPGA

A Reconfigurable Architecture of a Scalable, Ultrafast, Ultrasound, Delay-and-Sum Beamformer

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