Delay fault testing and silicon debug using scan chains

Datta, Ramyanshu; Sebastine, Antony; Abraham, Jacob A.

doi:10.1109/etsym.2004.1347600

Cited by 36 publications

(5 citation statements)

References 9 publications

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“…Prabhakar et al [15] proposed a logic implication based trace signals selection method. In addition, the use of scan chains in post-silicon debug has been extensively studied in [16], [17].…”

Section: Circuit Buffer Widthmentioning

confidence: 99%

Feature-based Signal Selection for Post-silicon Debug using Machine Learning

Rahmani

Mishra

2017

IEEE Trans. Emerg. Topics Comput.

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A key challenge of post-silicon validation methodology is to select a limited number of trace signals that are effective during post-silicon debug. Structural analysis used by traditional signal selection techniques are fast but lead to poor restoration quality. In contrast, simulation-based selection techniques provide superior restorability but incur significant computation overhead. While early work on machine learning based signal selection is promising [1], it is still not applicable on large industrial designs since it needs thousands of simulations of large and complex designs. In this paper, we propose a signal selection technique that addresses the scalability issue of simulation-based techniques while maintaining a high restoration performance. The basic idea is to train a machine learning framework using a small set of circuits, and apply the trained model to the bigger circuit under test, without any need for simulating the large industry-scale designs. This paper makes two fundamental contributions: i) this is the first attempt to show that learning from small related circuits can be useful for signal selection, and ii) this is the first automated signal selection approach that is applicable on industrial designs without sacrificing restoration quality. Experimental results indicate that our approach can improve restorability by up to 135.4% (8.8% on average) while significantly reduce (up to 37X, 16.6X on average) the runtime compared to existing signal selection approaches.

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Section: Circuit Buffer Widthmentioning

confidence: 99%

Feature-based Signal Selection for Post-silicon Debug using Machine Learning

Rahmani

Mishra

2017

IEEE Trans. Emerg. Topics Comput.

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“…Scan-based debug is a known technique for post-silicon validation [3]- [6]. The sampled data is offloaded through scan chains and then it is analyzed using post-processing techniques, such as latch divergence analysis [7] or failure propagation tracing [8].…”

Section: Related Work and Motivationmentioning

confidence: 99%

Design-for-Debug Architecture for Distributed Embedded Logic Analysis

Kinsman

Nicolici

2011

IEEE Trans. VLSI Syst.

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In multi-core designs, distributed embedded logic analyzers with multiple trigger units and trace buffers with real-time offload capability through high-speed trace ports can be placed on-chip. This brings new challenges on how to connect the debug units together in such way that the limited storage space in the trace buffers can be used efficiently. This problem is further aggravated when shadow registers are used to capture data for some signals in the design. In this paper, we propose a new architecture that can dynamically allocate the trace buffers at runtime based on the needs for debug data acquisition coming from multiple data sources and user-programmable priorities. Experimental results show that using the proposed architecture, real-time observability can be improved using only a small amount of on-chip logic hardware, while avoiding excessive storage on-chip.Index Terms-Design-for-debug, distributed embedded logic analysis, post-silicon validation, real-time observability.

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“…On-chip path delay time measurement is one of the best alternatives to solve these problems. By measuring delay time of the path under measurement (PUM), not only the gross and small-delay faults can be detected but also the amount of timing violation in the failing paths can be obtained under certain environment conditions [10], [11]. However, on-chip delay measurement incurs high test cost because it uses scan design, which brings about long test application time due to scan shift operation.…”

Section: Introductionmentioning

confidence: 99%

Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement

Zhang

Namba

Ito

2014

IEICE Trans. Inf. & Syst.

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SUMMARYIn recent VLSIs, small-delay defects, which are hard to detect by traditional delay fault testing, can bring about serious issues such as short lifetime. To detect small-delay defects, on-chip delay measurement which measures the delay time of paths in the circuit under test (CUT) was proposed. However, this approach incurs high test cost because it uses scan design, which brings about long test application time due to scan shift operation. Our solution is a test application time reduction method for testing using the on-chip path delay measurement. The testing with on-chip path delay measurement does not require capture operations, unlike the conventional delay testing. Specifically, FFs keep the transition pattern of the test pattern pair sensitizing a path under measurement (PUM) (denoted as p) even after the measurement of p. The proposed method uses this characteristic. The proposed method reduces scan shift time and test data volume using test pattern merging. Evaluation results on ISCAS89 benchmark circuits indicate that the proposed method reduces the test application time by 6.89∼62.67% and test data volume by 46.39∼74.86%.

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Delay fault testing and silicon debug using scan chains

Cited by 36 publications

References 9 publications

Feature-based Signal Selection for Post-silicon Debug using Machine Learning

Feature-based Signal Selection for Post-silicon Debug using Machine Learning

Design-for-Debug Architecture for Distributed Embedded Logic Analysis

Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement

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