2023
DOI: 10.35940/ijitee.d9475.0312423
|View full text |Cite
|
Sign up to set email alerts
|

Delay-Optimistic Multiplier Design using Parallel Prefix Adder with Compressors

Abstract: This article provides an illustration of the design process for 5-2 and 7-2 compressors operating at extremely high speeds. When compared to the prior designs, the new approach significantly reduced the gate-level delay while maintaining an appropriate overall transistor and gate count. With the help of 7:2 and 5:2 compressor infusion, when compared to earlier designs, the gate-level latency has been significantly decreased while the overall transistor and gate counts have remained within acceptable bounds. Th… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
0
0

Publication Types

Select...

Relationship

0
0

Authors

Journals

citations
Cited by 0 publications
references
References 16 publications
0
0
0
Order By: Relevance

No citations

Set email alert for when this publication receives citations?