Delay streams for graphics hardware

AilaTimo,; MiettinenVille,; NordlundPetri,

doi:10.1145/882262.882347

Cited by 41 publications

(10 citation statements)

References 41 publications

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“…Beginning with a fixedfunction pipeline with configurable parameters, user programmability began in the form of register combiners, expanded to programmable vertex and fragment shaders (e.g., Cg [Mark et al 2003]), and today encompasses tessellation, geometry, and even generalized compute shaders in Direct3D 11. Recent research has also proposed programmable hardware stages beyond shading, including a delay stream between the vertex and pixel processing units [Aila et al 2003] and the programmable culling unit [Hasselgren and Akenine-Möller 2007].…”

Section: Programmable Graphics Abstractionsmentioning

confidence: 99%

Piko

et al. 2015

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InputStage A Stage B Stage C Stage D Piko Frontend Pipeline Schedule Pipeline Description Spatial Bins Multicore CPU Manycore GPU Piko Backend Figure 1: Piko is a framework for designing and implementing programmable graphics pipelines that can be easily retargeted to different application configurations and architectural targets. Piko's input is a functional and structural description of the desired graphics pipeline, augmented with a per-stage grouping of computation into spatial bins (or tiles), and a scheduling preference for these bins. Our compiler generates efficient implementations of the input pipeline for multiple architectures and allows the programmer to tweak these implementations using simple changes in the bin configurations and scheduling preferences. AbstractWe present Piko, a framework for designing, optimizing, and retargeting implementations of graphics pipelines on multiple architectures. Piko programmers express a graphics pipeline by organizing the computation within each stage into spatial bins and specifying a scheduling preference for these bins. Our compiler, Pikoc, compiles this input into an optimized implementation targeted to a massively-parallel GPU or a multicore CPU. Piko manages work granularity in a programmable and flexible manner, allowing programmers to build load-balanced parallel pipeline implementations, to exploit spatial and producer-consumer locality in a pipeline implementation, and to explore tradeoffs between these considerations. We demonstrate that Piko can implement a wide range of pipelines, including rasterization, Reyes, ray tracing, rasterization/ray tracing hybrid, and deferred rendering. Piko allows us to implement efficient graphics pipelines with relative ease and to quickly explore design alternatives by modifying the spatial binning configurations and scheduling preferences for individual stages, all while delivering real-time performance that is within a factor six of state-of-the-art rendering systems.

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Section: Programmable Graphics Abstractionsmentioning

confidence: 99%

Piko

et al. 2015

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“…As a result, researchers have proposed several modifications to current graphics pipelines [Aila et al 2003;Sugerman et al 2009]. These theoretical systems are heuristic but difficult to implement on current graphics hardware up to now.…”

Section: Related Workmentioning

confidence: 99%

Coherent depth test scheme in FreePipe

Liu

Huang

et al. 2010

Proceedings of the 9th ACM SIGGRAPH Conference on Virtual-Reality Continuum and Its Applications in Industry

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This paper presents a rasterization rendering pipeline namely FreePipe. The system builds a bridge between the traditional graphics pipelines and the general purpose computing architecture CUDA by taking advantages of both sides. The core of FreePipe is a z-buffer based rasterizer entirely implemented in CUDA. The graphics pipeline can be easily mapped to the CUDA programming model with each stage fully open to the programmers. Within this flexible architecture, we propose a coherent depth test scheme for concurrent capture of both depth and color attributes using the atomicCAS operation in CUDA. The scheme can be easily extended to multiple level for efficient rendering of order independent transparency, which has significant performance improvement over the state-of-the-art methods based on traditional graphics pipelines.

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“…Other work on mobile graphics include Akenine-Möller and Ström's work on anti-aliasing, texture filtering, and occlusion culling that are suitable for low-power graphics hardware 21 and Aila et al's work on delay streams for hardware-assisted occlusion culling. 22 Kameyama et al describe a very low-power accelerator for geometry processing and rasterization that has been used in some mobile phones in Japan. 23 There is already a large offering of mobile graphics hardware from even larger number of vendors than on desktop.…”

Section: Hardware Designsmentioning

confidence: 99%

New APIs for mobile graphics

Pulli

2006

SPIE Proceedings

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Progress in mobile graphics technology during the last five years has been swift, and it has followed a similar path as on PCs: early proprietary software engines running on integer hardware paved the way to standards that provide a roadmap for graphics hardware acceleration. In this overview we cover five recent standards for 3D and 2D vector graphics for mobile devices. OpenGL ES is a low-level API for 3D graphics, meant for applications written in C or C++. M3G (JSR 184) is a high-level 3D API for mobile Java that can be implemented on top of OpenGL ES. Collada is a content interchange format and API that allows combining digital content creation tools and exporting the results to different run-time systems, including OpenGL ES and M3G. Two new 2D vector graphics APIs reflect the relations of OpenGL ES and M3G: OpenVG is a low-level API for C/C++ that can be used as a building block for a high-level mobile Java API JSR 226.

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Delay streams for graphics hardware

Cited by 41 publications

References 41 publications

Piko

Piko

Coherent depth test scheme in FreePipe

New APIs for mobile graphics

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