Deletion Error Correction based on Polar Codes in Skyrmion Racetrack Memory

Sun, He; Liu, Rongke; Tian, Kuangda; Zou, Tong; Feng, Baoping

doi:10.1109/wcnc49053.2021.9417534

Cited by 4 publications

(3 citation statements)

References 9 publications

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“…Conventional Forward error correction schemes are also explored for positional errors, especially in the domain of DNA storage [26]. Recent examples are Low-density parity-check codes (LDPC) [9] and polar codes [10] which are applied to insertion and deletion channels like racetrack. In [9], authors present a new coding scheme that can effectively decode corrupted data with non-iterative detection.…”

Section: Error Correction With Fecmentioning

confidence: 99%

“…In [10], authors build two typical error-correction models for the skyrmion memory and a polar coding scheme for error-correction is applied, whereas the proposed successive-cancellation decoding algorithm is used to correct the deletion errors. Authors propose an efficient decoding algorithm to improve the decoding performance and reduce the decoding complexity of polar codes in insertion deletion channels.…”

Section: Error Correction With Fecmentioning

confidence: 99%

“…As such, an n-racetracks array would require an n-bit error correcting code, that exposes severe scalability challenges of this approach. Recently, complex coding schemes including Low-density-parity-codes [9] and Polar codes [10] were applied to large data blocks stored on the Racetrack arrays to mitigate deletion and insertion errors. However, these codes are known to be associated with high implementation costs.…”

Section: Introductionmentioning

confidence: 99%

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On the Positional Single Error Correction and Double Error Detection in Racetrack Memories

et al. 2023

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In the era of non-volatile memories, the racetrack memory is a promising technology to pack hundreds of bits in a magnetic nanowire. A solid-state read head is grown alongside the nanowire to sense individual bits which are pushed across the head by a shifting force. However, the probabilistic nature of this shifting movement inflicts positional errors. Therefore, robust and low-cost error correcting codes are essential for a reliable alternative in on-chip memories and storage applications. Recent works focus on Varshamov-Tenengolts (VT) codes which can correct all single bit insertions and deletions. However, VT codes are incapable of detecting multiple deletions/insertions. Because a positional error corrupts multiple data words, multi-bit positional error detection is critical for racetrack memories. In this article, we propose a novel positional single error correction and double error detection (P-SECDED) code in the context of racetrack memories with a single read head. In particular, we adopt a postamble-based approach where a VT-encoded codeword appends a carefully selected bit-pattern, stored on the racetrack. We rigorously analyze the limitations of the postamble method, and deduce a criterion for postamble selection. We further provide a methodology to optimize this postamble selection in order to correct all single-bit errors and as much of two-bit errors as possible. Finally, we prove that all incurable two-bit errors are successfully detected. To the best of our knowledge, this work is the first attempt to provide P-SECDED fault-tolerance to three-dimensional racetrack memories which cannot afford multiple read heads.

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