Delta-Measurement Low-Power SAR ADC Architecture with Adaptive Threshold-First Switching

Ding, Zhaoming; Zhou, Xiong; Li, Qiang

doi:10.1109/iscas.2018.8351179

Cited by 2 publications

(1 citation statement)

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“…Hogenauer structure and simple FIR filters [3]. However, the flip-side can be a substantial increase of power dissipation [4]. Moreover, in sensor readout interfaces, reconfigurable ADCs that provide different sampling and resolution options, are especially useful, where the ADC is time-multiplexed to digitize different types of input signal with different bandwidth and resolution requirements [5].…”

Section: Introductionmentioning

confidence: 99%

A Reconfigurable Dual-Mode Tracking SAR ADC without Analog Subtraction

Safarpour

Inanlou

Silvén

et al. 2019

2019 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA)

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In this contribution, it is proposes to limit the quantization search space of a successive approximation analogto-digital converter through an analytic derivation of maximum possible sample-to-sample variation. The presented example design of the proposed ADC is an 8-bit 1MS/s ADC with SAR logic customized to incorporate this priori information while no modification has been required to the analog circuitry. In comparison to conventional SAR conversion, the proposed tracking approach yields significant reduction in total power consumption in oversampling mode. The power savings are due to the reduced number of SAR cycles, and voltage variation minimization across DAC capacitors. The design is reconfigurable both to conventional SAR sampling and the proposed tracking scheme. The approach is attractive for SAR ADCs embedded in very low power micro-controllers.

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Section: Introductionmentioning

confidence: 99%