Delta-sigma modulator based mixed-signal BIST architecture for SoC

Ong, Chee-Kian; Cheng, Kwang-Ting; Wang, Li-C.

doi:10.1145/1119772.1119922

Cited by 15 publications

(5 citation statements)

References 19 publications

(21 reference statements)

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“…The histogram method used in the scheme also requires much larger overhead for additional memory space for storing data. Ong et al [12] give a second-order delta-sigma modulator based mixed-signal BIST architecture capable of testing/characterizing itself using all digital stimulus. Test time of the architecture is shorter than the static linear ramp testing.…”

Section: Bist Solutionsmentioning

confidence: 99%

“…A common implementation of such decimation is comb filter, or sometimes called sinc filter that will also eliminate the unnecessary high frequency portions of the bit-stream. Ong et al [12] give an efficient implementation of a comb filter by cascading K stages of accumulators operating at the sampling rate of the sigma-delta modulator, followed by K stages of cascaded differentiators operating at the down-sampled rate. The transfer function of the sinc filter with K stages and a down-sample ratio M has the form:…”

Section: Digital Filtersmentioning

confidence: 99%

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Built-in Self-Calibration of On-chip DAC and ADC

Jiang

Agrawal

2008

2008 IEEE International Test Conference

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Abstract-Linearity measurements are significant for assessing the performance of a modern mixed-signal system-on-chip. In this paper a new built-in self-test (BIST) scheme is presented for testing and calibration of on-chip high-resolution digitalto-analog converters (DACs) and analog-to-digital converters (ADCs) for better linearity using sigma-delta modulator and low-resolution dithering DAC. Ramp signals are used as testing stimuli and responses of DAC-under-test (DUT) are measured by a first-order 1-bit sigma-delta modulator with high oversampling rate (OSR) and a low-pass digital filter for noise cancellation. A polynomial fit algorithm is used to characterize DAC and to obtain calibrating coefficients that determine whether the DUT passes or fails the test. DUT output error is compensated for by a dithering DAC with dynamic element matching (DEM) technique, which is controlled by the calibrating coefficients, to reduce the integral non-linearity (INL) error. Simulation results show that a sigma-delta modulator with effective number of bits (ENOB) equivalent to 17-bit ADC and a 6-bit low-cost dithering DAC are sufficient to calibrate a 14-bit high-resolution on-chip DAC such that the maximum INL error is reduced from 3 LSB to approximate 0.25 LSB. Testing and calibration of on-chip ADC using the same scheme is also discussed.

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Section: Bist Solutionsmentioning

confidence: 99%

Section: Digital Filtersmentioning

confidence: 99%

Built-in Self-Calibration of On-chip DAC and ADC

Jiang

Agrawal

2008

2008 IEEE International Test Conference

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“…Sehgal et al [13] optimized TAMs and test scheduling for mixed-signal SoCs. Tofte et al [14] and Ong et al [9] proposed built-in-self-test (BIST) for mixed-signal SoC's using a second-order delta sigma modulator, and an on-chip DSP for generating the digital test stimulus.…”

Section: Prior Workmentioning

confidence: 99%

An area efficient mixed-signal test architecture for systems-on-a-chip

Venkatanarayanan

Bushnell

2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

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“…Among the various approaches for the implementation of BIST scheme, loopback test method has been proposed as an efficient solution [5], and various DfT circuitries for the loopback test schemes have been proposed [6]- [9]. However most mixed-signal BIST approaches including loopback test have not been proposed for the issues in the differential signaling due to the following reasons.…”

Section: Introductionmentioning

confidence: 99%

Transformer-Coupled Loopback Test for Differential Mixed-Signal Specifications

Kim

Fu²,

Abraham

2007

25th IEEE VLSI Test Symmposium (VTS'07)

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Loopback tests for a differential mixed-signal Device Under Test (DUT) have rarely been attempted, since any imbalance introduced by a Design for Test (DfT) circuitry on differential signaling delivers an imperfect sinusoidal wave to the DUT input, thereby degrading the DUT performance. In addition, this methodology inherently suffers from fault masking. These problems result in low test accuracy and serious yield loss. This paper presents a novel methodology for efficient prediction of individual DUT dynamic performance parameters with a Radio-Frequency (RF) transformer in loopback mode to overcome the imbalance problem of DfT circuitry. Cascaded RF transformer in loopback mode produces differently weighted loopback responses, which are used to characterize the DUT dynamic performance. Hardware measurement results show that this approach can be effectively used to predict the specifications of a DUT.

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Delta-sigma modulator based mixed-signal BIST architecture for SoC

Cited by 15 publications

References 19 publications

Built-in Self-Calibration of On-chip DAC and ADC

Built-in Self-Calibration of On-chip DAC and ADC

An area efficient mixed-signal test architecture for systems-on-a-chip

Transformer-Coupled Loopback Test for Differential Mixed-Signal Specifications

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