Demonstrating production quality multiple exposure patterning aware routing for the 10NM node

Liebmann, Lars W.; Gerousis, Vassilios; Gutwin, Paul; Zhang, Mike; Han, Geng; Cline, Brian

doi:10.1117/12.2045958

Cited by 8 publications

(4 citation statements)

References 6 publications

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“…As noted in [13], placement of vias next to each other is not allowed in advanced nodes. That is, as via pitches are larger (e.g., by a √ 2 factor) than metal pitches, placement of a via at a particular location blocks horizontally and vertically adjacent locations, and sometimes diagonally adjacent locations as well.…”

Section: Routing Rule Formulationmentioning

confidence: 98%

“…To scale semiconductor process nodes below the resolution limits of 193i optical lithography, multi-patterning techniques (e.g., litho-etch-litho-etch (LELE) and self-aligned double and quadruple patterning (SADP, SAQP) [13] have already been widely used in production. Multi-patterning is expected to be the basis of mainstream process offerings through the foundry 10nm and even 7nm nodes, and will persist even with deployment of extreme ultraviolet (EUV) lithography [10].…”

Section: Introductionmentioning

confidence: 99%

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Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router

Han

Kahng

Lee

2015

Proceedings of the 52nd Annual Design Automation Conference

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Continued technology scaling with more pervasive use of multipatterning has led to complex design rules and increased difficulty of maintaining high layout densities. Intuitively, emerging constraints such as unidirectional patterning or increased via spacing will decrease achievable density of the final place-and-route solution, worsening die area and product cost. However, no methodology exists for accurate assessment of design rules' impact on physical chip implementation. At the same time, this is a crucial need for early development of BEOL process technologies, particularly with FinFET or future vertical-device architectures where cell footprints can become much smaller than in bulk planar CMOS technologies. In this work, we study impacts of patterning technology choices and associated design rules on physical implementation density, with respect to cost-optimal design rule-correct detailed routing. A key contribution is an Integer Linear Programming (ILP) based optimal router (OptRouter) which considers complex design rules that arise in sub-20nm process technologies. Using OptRouter, we assess wirelength and via count impacts of various design rules (implicitly, patterning technology choices) by analyzing optimal routing solutions of clips (i.e., switchbox instances) extracted from post-detailed route layouts in an advanced technology.

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Section: Routing Rule Formulationmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router

Han

Kahng

Lee

2015

Proceedings of the 52nd Annual Design Automation Conference

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“…With field of narrow and wide width features, we may observe issues with the cutmask resulting in shorts or opens in addition to showing width variability. It was found in [5] that a move to a cutmask that looks like a via mask with fixed size cuts could improve manufacturability at the expense of coupling capacitance increase.…”

Section: Spacer-based Multiple Coloringmentioning

confidence: 98%

Design and technology co-optimization near single-digit nodes

Liebmann¹,

Topaloglu²

2014

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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As we approach single-digit nodes, traditional design for manufacturability is augmented through several methodologies and design paradigms such as design-technology cooptimization (DTCO), systematic yield limiters optimization (SYLO), and design retargeting. We discuss triple-patterning and spacer-based multiple patterning and their design implications as these technologies will be necessary to cruise us to single-digit nodes. With the help of DTCO, there seems to be a clear path to sub-10nm with or without extreme ultra-violet lithography.

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“…The same-color via pitch is defined as the minimum center-to-center distance of a pair of via patterns from the same via layer that can be assigned to the same mask in TPL layout decomposition. By applying SADP on metal layers and TPL on via layers in layout manufacturing, the same-color via pitch is slightly larger than two times of routing track pitch size Lars Liebmann et al (2014). As shown in Figure 5.2(a), suppose a via from a routed net is inserted in the center of the grid.…”

Section: Resultsmentioning

confidence: 99%

Design for Manufacturability in Advanced Lithography Technologies

Ding

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Demonstrating production quality multiple exposure patterning aware routing for the 10NM node

Cited by 8 publications

References 6 publications

Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router

Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router

Design and technology co-optimization near single-digit nodes

Design for Manufacturability in Advanced Lithography Technologies

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