Demonstration of a Fast, Low-Voltage, III-V Semiconductor, Non-Volatile Memory

Abstract

ULTRARAM™ is a III-V semiconductor memory technology which exploits resonant tunneling to allow ultra-low-energy memory logic switching (per unit area), whilst retaining non-volatility. Single-cell memories developed on GaAs substrates with a revised design and atomic-layer-deposition Al 2 O 3 gate dielectric demonstrate significant improvements compared to prior prototypes. Floating-gate (FG) memories with 20-µm gate length show 0/1 state contrast from 2.5-V program-read-erase-read (P/E) cycles with 500-µs pulse duration, which would scale to sub-ns switching speed at 20-nm node. Nonvolatility is confirmed by memory retention tests of 4×10 3 s with both 0 and 1 states completely invariant. Single cells demonstrate promising endurance results, undergoing 10 4 cycles without degradation. P/E cycling and disturbance tests are performed using half-voltages (±1.25 V), validating the high-density random access memory (RAM) architecture proposed previously. Finally, memory logic is retained after an equivalent of >10 5 P/E disturbances.

Simulations of resonant tunnelling through InAs/AlSb heterostructures for ULTRARAM™ memory

“…The remarkable performance characteristics of ULTRARAM™ are predicted by detailed simulations of quantum transport [7], and encouraging results have been demonstrated in single devices and 2 × 2 arrays at room temperature on GaAs substrates at 20 µm gate lengths [8], with implementation on Si substrates on-going [9]. Moreover, recent experimental results validate our previous simulation work, including the proposed half-voltage architecture for random access memory (RAM) applications [10]. Our previous theoretical investigations were for a specific layer thickness configuration of the triple-barrier InAs/AlSb tunnelling junction [7].…”

“…We conclude that this is not part of the ULTRARAM™ tunnelling mechanism and is an artefact of the simulation construction. Indeed, experimental studies support this assertion [8][9][10]19]. The peaks occurring at higher voltages are the expected resonant tunnelling peaks (figures 3(b) and (c)).…”

“…Lastly, is the sharpness of the onset of the peaks; a significant tunnelling current away from the P/E peak voltage will also cause logic disturbances [7]. It can be seen in figure 3 that the resonant tunnelling current forms sharp peaks at a little over 1 V, indicating that the TBRT structure is highly suitable for the implementation of FG memory, as demonstrated in experimental work to date [5,[8][9][10]. The simulations are repeated under the same conditions for each of the structures listed in table 1 for the program cycle, and are shown in figure 4.…”

“…Electrons which tunnel into the FG are trapped there indefinitely by the 2.1 eV barrier on one side (InAs/AlSb heterojunction), and an oxide gate dielectric with a high energy barrier on the other. In previous works [8][9][10], we have used 15 nm of Al 2 O 3 , providing an electron barrier of 3.1 eV [11], and requiring a gate voltage of 2.5 V to initiate P/E tunnelling through the TBRT structure. The choice of gate dielectric is somewhat arbitrary and can be tuned to give the desired memory performance.…”

“…Although the peaks reside at a much lower energy, corresponding to millisecond storage times at room temperature for localization energies of that size [17], the probability of transmission is very low, making it unlikely that these peaks impact on the retention capability of the memory. Indeed, fabricated devices show stable memory retention exceeding 24 h at 300 K with little or no state decay [8,10].…”