Demonstration of Conductive Bridging Random Access Memory (CBRAM) in Logic CMOS Process

Abstract

INTRODUCTIONOne of the promising technologies under development for next generation non-volatile memory is the Conductive Bridging Random Access Memory (CBRAM) which utilizes the reversible switching of an electroresistive dielectric between two conductive states as means of storing logical data [1][2][3][4][5]. In this paper, we describe the successful integration of CBRAM technology into an industry standard logic process. Moreover, we show functional operation of such a fully CMOS integrated CBRAM memory array and highlight its specific fundamental low power characteristics that make it suitable to be used in scaled embedded application as well as discrete devices. BACKGROUND AND EXPERIMENTSCBRAM technology is known by other names such as programmable metallization cell (PMC) solid electrolyte memory, nano-ionic resistive memory, electrochemical memory (ECM). The operational principle of CBRAM technology is based on a reversible creation of an electrochemically induced nanoscale conductive link in a special dielectric acting as a ion conducting solid-electrolyte. In its simplest implementation, the basic storage element consists of an access transistor and a programmable resistor (similar to the DRAM one transistor and one capacitor cell). We have successfully integrated this resistive memory in 180nm with Aluminum back-end-of-line (BEOL) as well as 130nm with Copper BEOL logic processes ( Fig. 1 & 2). Cross section image of a fully integrated 1T1R cells are shown in these figures. The programmable elements required only 2 non critical masks at BEOL steps. In this paper, we present basic characterization results on 180nm and 130nm logic CMOS integrated CBRAM memory arrays. We explore the operational capability of the core technology including sub 100ns write, data sheet operation at 1V, multi-level cell capability as well as retention and reliability characteristics. Data was collected on single cells as well as fully integrated decoded arrays. RESULTS AND DISCUSSIONThe DC or quasi static current voltage characteristics in Fig. 3 shows that as the voltage across the storage resistor is swept, the device is initially at high resistance state and switches on upon reaching a certain threshold voltage. Here, a current compliance of 10μA prevents the resistance to increase in a runaway effect. When the voltage is swept back, the storage dielectric is shown to be in the conductive state. A dynamic range of 10,000 is shown in this graph. This conductive state is a function of the program current and can be controlled accurately rendering multi-level cell possibility for this technology. Figure 3b shows the dependence of resistance state on programming current. This allows for potential use of this technology in multi-level cell (MLC) implementation. The threshold voltage can be tuned by process and operational parameters to fit seamlessly in a standard logic process. To erase the cell, the voltage is swept back in the negative direction and the high resistance state is recovered.A critical aspects of a new technology...

Appearance of quantum point contact in Pt/NiO/Pt resistive switching cells

“…On the other hand, RS memories consisting of both one active (oxidizable) electrode such as Ag or Cu and the counter inert electrode such as Pt or TiN are widely known as conductive bridging random access memories (CBRAMs). 11 When a positive voltage is applied to the active electrode, dissolution and ionization of the active metal and bridging of a metallic conductive filament to the opposite inert electrode through the TMO layer. The metal ions move toward the active electrode and the filament is eventually ruptured by application of a negative voltage to the active electrode.…”

Total-ionizing-dose effects on the impedance of silverdoped chalcogenide programmable metallization cells

“…In CBRAM products, PMCs are implemented in the back-endof-line (BEOL) of a CMOS process (see Fig. 1a) [11], enabling the use of this technology as a standalone memory microcircuit or as an embedded memory [13]- [16]. from [17].…”

A High Performance and Low Power Logic CMOS Compatible Embedded 1Mb CBRAM Non-Volatile Macro

“…Low resistance state is typically called the SET state and high resistance stat is called the RESET state. Previously, we reported the process technology details of an integrated CBRAM cell in 180nm (aluminum BEOL) and 130nm (Cu BEOL) logic process [5]. Previously, we reported on the physics of the CBRAM cell operation as well as demonstrated 100,000 write cycles and 10 years data retention for this technology [5].…”

“…Previously, we reported the process technology details of an integrated CBRAM cell in 180nm (aluminum BEOL) and 130nm (Cu BEOL) logic process [5]. Previously, we reported on the physics of the CBRAM cell operation as well as demonstrated 100,000 write cycles and 10 years data retention for this technology [5]. In this paper, we focus on design aspects of CBRAM and present performance and power characteristics of a yielding 1Mb CBRAM memory module integrated in standard 130nm Logic process and highlight some key design features.…”

“…The total area of the bit cell in this work is 22F 2 and is determined exclusively by the design rules for the access transistor and is scalable with technology node. The CBRAM bit cell has been demonstrated down to 8F 2 cell along with multi-level cell capability [4][5]. Due to combination of core CBRAM technology, architecture, and design, the voltages required are all well below the supply voltage thus eliminating the need for charge pumps as commonly needed in flash designs [1,6].…”