Demonstration of Single-Flux-Quantum 64-B Lookup Table With Cryo-CMOS Decoders for Reconfiguration

Hironaka, Yuki; Hosoya, Takuya; Yamanashi, Yuki; Yoshikawa, Nobuyuki

doi:10.1109/tasc.2022.3191984

Cited by 3 publications

(3 citation statements)

References 17 publications

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“…This makes RSFQ systems more power-efficient than current technologies. Many studies focus on RSFQ technology, covering circuit and system designs [4][5][6], layout designs [7,8], as well as electronic design automation (EDA) tools and algorithms [9,10].…”

Section: Introductionmentioning

confidence: 99%

High-density superconductive logic circuits utilizing 0 and π josephson junctions

Razmkhah,

Pedram

2024

Eng. Res. Express

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Superconductor Electronics (SCE) is a fast and power-efficient technology with great potential for overcoming conventional CMOS electronics' scaling limits. Nevertheless, the primary challenge confronting SCE today is its integration level, which lags several orders of magnitude behind CMOS circuits. In this study, we have innovated and simulated a novel logic family grounded in the principles of phase shifts occurring in 0 and π Josephson junctions. The fast phase logic (FPL) eliminates the need for large inductor loops and shunt resistances by combining the half-flux and phase logic. Therefore, the Josephson junction (JJ) area only limits the integration density. The cells designed with this paradigm are fast, and the clock-to-Q delay for logic cells is about 4ps. While maintaining over 50% parameter margins for wiring cells. This logic is power efficient and can increase the integration by at least 100 times in the SCE chips.

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Section: Introductionmentioning

confidence: 99%

High-density superconductive logic circuits utilizing 0 and π josephson junctions

Razmkhah,

Pedram

2024

Eng. Res. Express

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“…We had previously developed a superconductor memory cell that could be reconfigured by applying external control currents and read out by inputting an SFQ clock. 23,24) For this memory cell, highspeed nondestructive read-out at frequencies beyond 50 GHz was possible through SFQ read-out. However, its reconfiguration speed was less because of the use of external control currents.…”

mentioning

confidence: 99%

“…We also demonstrated the operation of superconductor LUTs composed of our proposed 4-bit and 64-bit memory cell arrays. 23,24) However, for building a large-scale LUT, in addition to advanced circuit-fabrication process, reduction in the footprint of the memory cell used in the LUT is also necessary. In a previous study, we used a non-destructive read-out flip-flop (NDRO) with interface circuits, called magnetically coupled DC/SFQ converter (MC-DC/SFQ), as the memory cell.…”

mentioning

confidence: 99%

Reconfiguration of nondestructively readable superconductor memory by direct injection of magnetic flux to storage loop

Yamanashi

Hosoya

YOSHIKAWA

2023

Appl. Phys. Express

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In this study, we demonstrate a novel method for the reconfiguration of a nondestructively readable memory cell for superconductor integrated circuits. The proposed reconfiguration method involves the direct injection of flux quantum to the storage loop of the memory cell, which has been achieved using interface circuits in the previous studies. By applying this method, the footprint of the superconductor memory cell can be reduced by half. We experimentally demonstrate the proof-of-concept of the investigated reconfiguration method. We expect that the memory cell reconfigured using the proposed method will be suitable for building large-scale lookup tables using superconductor circuits.

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Superconductor Logic Implementation With All-JJ Inductor-Free Cell Library

Cong,

Razmkhah,

Karamuftuoglu

et al. 2024

IEEE Trans. Appl. Supercond.

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Demonstration of Single-Flux-Quantum 64-B Lookup Table With Cryo-CMOS Decoders for Reconfiguration

Cited by 3 publications

References 17 publications

High-density superconductive logic circuits utilizing 0 and π josephson junctions

High-density superconductive logic circuits utilizing 0 and π josephson junctions

Reconfiguration of nondestructively readable superconductor memory by direct injection of magnetic flux to storage loop

Superconductor Logic Implementation With All-JJ Inductor-Free Cell Library

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