DeNovoND: Efficient Hardware for Disciplined Nondeterminism

Sung, Hyojin; Komuravelli, Rakesh; Adve, Sarita V.

doi:10.1109/mm.2014.5

Cited by 22 publications

(38 citation statements)

References 19 publications

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“…DeNovo is an ongoing research project seeking to broaden the class of software supported by such simple protocols. Recently, we extended DeNovo to support disciplined lock-based programs using dynamically generated access signatures to guide self-invalidations Sung et al 2013Sung et al , 2014. These extensions are rather small, and we believe can be verified independently.…”

Section: Redesigning Hardware Coherence Protocolsmentioning

confidence: 99%

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Revisiting the Complexity of Hardware Cache Coherence and Some Implications

Komuravelli

Adve

Chou

2014

ACM Trans. Archit. Code Optim.

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Cache coherence is an integral part of shared-memory systems but is also widely considered to be one of the most complex parts of such systems. Much prior work has addressed this complexity and the verification techniques to prove the correctness of hardware coherence. Given the new multicore era with increasing number of cores, there is a renewed debate about whether the complexity of hardware coherence has been tamed or whether it should be abandoned in favor of software coherence. This article revisits the complexity of hardware cache coherence by verifying a publicly available, state-of-the-art implementation of the widely used MESI protocol, using the Murϕ model checking tool. To our surprise, we found six bugs in this protocol, most of which were hard to analyze and took several days to fix. To compare the complexity, we also verified the recently proposed DeNovo protocol, which exploits disciplined software programming models. We found three relatively easy to fix bugs in this less mature protocol. After fixing these bugs, our verification experiments showed that, compared to DeNovo, MESI had 15X more reachable states leading to a 20X increase in verification (model checking) time. Although we were eventually successful in verifying the protocols, the tool required making several simplifying assumptions (e.g., two cores, one address). Our results have several implications: (1) they indicate that hardware coherence protocols remain complex;(2) they reinforce the need for protocol designers to embrace formal verification tools to demonstrate correctness of new protocols and extensions; (3) they reinforce the need for formal verification tools that are both scalable and usable by non-expert; and (4) they show that a system based on hardware-software co-design can offer a simpler approach for cache coherence, thus reducing the overall verification effort and allowing verification of more detailed models and protocol extensions that are otherwise limited by computing resources.

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Section: Redesigning Hardware Coherence Protocolsmentioning

confidence: 99%

“…DPJ and DeNovo are ongoing projects that continue to incorporate support for increasingly wider classes of programs Heumann et al 2013;Sung et al 2013Sung et al , 2014. We discuss this ongoing work and implications for general codes in Section 5.…”

Section: Denovomentioning

confidence: 99%

Revisiting the Complexity of Hardware Cache Coherence and Some Implications

Komuravelli

Adve

Chou

2014

ACM Trans. Archit. Code Optim.

Self Cite

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“…The bloom filters are reset only on barriers, which decreases their efficiency. DeNovoND [36] performs selective self-invalidation upon lock synchronization, using a hardware queue lock. However, both proposals have the drawback of (i) trading information accuracy for reducing hardware support and (ii) incurring very expensive self-invalidation since all cache tags must be matched against the filter.…”

Section: Related Workmentioning

confidence: 99%

A Dual-Consistency Cache Coherence Protocol

Ros

Jimborean

2015

2015 IEEE International Parallel and Distributed Processing Symposium

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Abstract-Weak memory consistency models can maximize system performance by enabling hardware and compiler optimizations, but increase programming complexity since they do not match programmers' intuition. The design of an efficient system with an intuitive memory model is an open challenge. This paper proposes SPEL, a dual-consistency cache coherence protocol which simultaneously guarantees the strongest memory consistency model provided by the hardware and yields improvements in both performance and energy consumption. The design of the protocol exploits a compile-time identification of code regions which can be executed under a less restrictive, thus optimized protocol, without harming correctness. Outside these regions, code is executed under a more restrictive protocol which enforces sequential consistency. Compared to a standard directory protocol, we show improvements in performance of 24% and reductions in energy consumption of 32%, on average, for a 64-core chip multiprocessor.

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“…DeNovo [43] exploits the data-race-freedom of disciplined programming models to eliminate the transient states of the cache coherence protocols, but requires additional hardware support for synchronization primitives [44]. Totoni et al [45] propose a runtime-guided mechanism to switch off cache banks using formal language theory to detect application phases.…”

Section: Runtime-aware Architecturesmentioning

confidence: 99%

Runtime-Guided Management of Scratchpad Memories in Multicore Architectures

Alvarez

Moretó

Casas

et al. 2015

2015 International Conference on Parallel Architecture and Compilation (PACT)

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Abstract-The increasing number of cores and the anticipated level of heterogeneity in upcoming multicore architectures cause important problems in traditional cache hierarchies. A good way to alleviate these problems is to add scratchpad memories alongside the cache hierarchy, forming a hybrid memory hierarchy. This memory organization has the potential to improve performance and to reduce the power consumption and the on-chip network traffic, but exposing such a complex memory model to the programmer has a very negative impact on the programmability of the architecture. Emerging task-based programming models are a promising alternative to program heterogeneous multicore architectures. In these models the runtime system manages the execution of the tasks on the architecture, allowing them to apply many optimizations in a generic way at the runtime system level. This paper proposes giving the runtime system the responsibility to manage the scratchpad memories of a hybrid memory hierarchy in multicore processors, transparently to the programmer. In the envisioned system, the runtime system takes advantage of the information found in the task dependences to map the inputs and outputs of a task to the scratchpad memory of the core that is going to execute it. In addition, the paper exploits two mechanisms to overlap the data transfers with computation and a locality-aware scheduler to reduce the data motion. In a 32-core multicore architecture, the hybrid memory hierarchy outperforms cache-only hierarchies by up to 16%, reduces on-chip network traffic by up to 31% and saves up to 22% of the consumed power.

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DeNovoND: Efficient Hardware for Disciplined Nondeterminism

Cited by 22 publications

References 19 publications

Revisiting the Complexity of Hardware Cache Coherence and Some Implications

Revisiting the Complexity of Hardware Cache Coherence and Some Implications

A Dual-Consistency Cache Coherence Protocol

Runtime-Guided Management of Scratchpad Memories in Multicore Architectures

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