Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors

Martínez, Carmen; Vallejo, Enrique; Beivide, Ramón; Izu, Cruz; Moretó, Miquel

doi:10.1007/s10766-006-0014-1

Cited by 28 publications

(19 citation statements)

References 22 publications

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“…In [1], [15], [16], [17], [18] and [19], it has been shown that hexagonal torus networks are a special family of EJ networks where the nodes of the graph are represented by EJ integers. A node <x, y> corresponds to a complex number x+yw where x, y are integers and w a complex number w= .…”

Section: Fig 1 Hexagonal Torus H4mentioning

confidence: 99%

“…Dense EJ networks are thus good candidate for NoC interconnection networks. It has been shown in [15], [16] the isomorphism between the dense EJ networks, hexagonal torus and Circulant graphs.…”

Section: Fig 1 Hexagonal Torus H4mentioning

confidence: 99%

“…Among the most popular NoC topologies developed for CMPs such as n-dimensional mesh, torus, folded torus, hypercube, and octagon, low-dimensional networks, like 2D-mesh and 2D-torus, offer better performance in terms of higher throughput and lower latency than highdimensional networks (high dimensional k-aryn-cubes and meshes) [13], [14]. Recently, two other wrap-around networks have been proposed as suitable alternatives to the 2D torus network: the degree 4 Gaussian networks [15], [16], [17] and the degree 6 Eisenstein-Jacobi (EJ) networks [17], [18], [19], [20]. In [1], the authors showed that EJ networks are generalizations of the hexagonal mesh topology developed earlier in [20], [21], and [22].…”

Section: Introductionmentioning

confidence: 99%

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All-To-All Broadcast in Hexagonal Torus Networks On-Chip

Touzene

2015

IEEE Trans. Parallel Distrib. Syst.

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Hexagonal torus networks are special family of Eisenstein-Jacobi (EJ) Networks which have gained popularity as good candidates network On-Chip (NoC) for interconnecting Multiprocessor System-on-Chips (MPSoCs). They showed better topological properties compared to the 2D torus networks with the same number of nodes. All-to-all broadcast is a collective communication algorithm used frequently in some parallel applications. Recently, an off-chip all-to-all broadcast algorithm has been proposed for hexagonal torus networks assuming half-duplex links and all-ports communication. The proposed all-to-all broadcast algorithm does not achieve the minimum transmission time and requires 24k extra buffers, where k is the network diameter. We first extend this work by proposing an efficient all-to-all broadcast on hexagonal torus networks under full-duplex links and all-ports communications assumptions which achieves the minimum transmission delay but requires 36k extra buffers per router. In a second stage, we develop a new all-to-all broadcast more suitable for hexagonal torus network on-chip that achieves optimal transmission delay time without requiring any extra buffers per router. By reducing the amount of buffer space, the new all-to-all broadcast reduces the routers cost which is an important issue in NoCs architectures.

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Section: Fig 1 Hexagonal Torus H4mentioning

confidence: 99%

Section: Fig 1 Hexagonal Torus H4mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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All-To-All Broadcast in Hexagonal Torus Networks On-Chip

Touzene

2015

IEEE Trans. Parallel Distrib. Syst.

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“…Applicable alternative regular topologies that have been shown to be suitable for on-chip networks include the mesh, ring and circulant graph topologies [18].…”

Section: B Distributed Test Vector Storagementioning

confidence: 99%

A distributed concurrent on-line test scheduling protocol for many-core NoC-based systems

Lee¹,

Mahapatra²,

Bhojwani

2009

2009 IEEE International Conference on Computer Design

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Abstract-Concurrent on-line testing (COLT) of manycore systems-on-chip (SoC) has been recently proposed by researchers in response to the growing threat of electronic wear-out to system operational lifetimes and to the increasing reliability and availability demands of safety-critical applications. Previous research in concurrent on-line testing has focused on centralized approaches to manage core testing while the system is available to execute normal user applications. However, as technology scaling allows dozens and hundreds of processing cores to be placed on a single chip, these centralized approaches are not scalable solutions. In this paper, a distributed concurrent on-line test scheduling protocol is proposed and evaluated against previously developed solutions. Our experiments show that a distributed COLT scheduler can test a moderately-sized SoC with a speedup of 3.85 over centralized approaches while consuming 84% less energy, and performance benefits improve as the number of cores per chip increases. This research also presents a core test ordering algorithm -Code-Division Core Test Scheduling -that provides an additional 40% reduction in system test latency compared to other schedulers. I. INTRODUCTIONRapid technology scaling has forced systems designers, reliability engineers and application programmers to rethink the fundamental design practices that have dominated computer system design for more than the past two decades. Multi-core systems-on-chip (SoC), with a handful of complex processing cores and integrated peripheral components, are predicted to be replaced by many-core SoC that contain hundreds or thousands of lightweight processing cores, memory and I/O subsystems. These many-core SoC will use packet switched networkson-chip (NoC) for inter-core communication, as opposed to the current standard of on-chip busses, [1,7]. Notable examples of this architecture include the 64-core TILE64 from TILERA [24] and the 80-core Intel Terascale SoC [11].As technology scaling has provided new opportunities for massively parallel and distributed computation to be performed on a single chip, new reliability challenges have also emerged. In addition to the well-understood circuit failures due to manufacturing imperfections, SoC components are also more susceptible to electronic wearout -permanent failures that emerge during use -as feature sizes scale below 65nm [2,6,7].In actuality, electronic wear-out is a combination of several physical degradation mechanisms, including electro-migration (EM), hot carrier injection (HCI) and negative bias temperature instability (NBTI), that are intensified by smaller feature sizes, higher current and power densities, and higher operating temperatures [2].Because the most significant electronic wear-out mechanisms manifest as an increasingly severe delay fault at the circuit level, many researchers have proposed the use of SCAN-based delay testing for detecting this type of error [4,14,15]. Built-in self-test (BIST) architectures using pseudo-randomly generated test v...

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“…For example, there is a Gaussian network with 200 nodes with diameter 10, whereas, any 2D toroidal network with 200 nodes will have a diameter of at least 15. There are many similarities between the Gaussian and EJ cases. We have tried to emphasize these connections when possible since the EJ networks are not well-understood compared to the significant work on Gaussian interconnection networks (for example, [17], [19], [20]). One reason for the scarcity of EJ results is that distance in EJ networks is more difficult to compute from the definition since the degree of each vertex is 6.…”

Section: Introductionmentioning

confidence: 99%

The Topology of Gaussian and Eisenstein-Jacobi Interconnection Networks

Flahive

Bose

2010

IEEE Trans. Parallel Distrib. Syst.

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Earlier authors have used quotient rings of Gaussian and Eisenstein-Jacobi integers to construct interconnection networks with good topological properties. In this paper, we present a unified study of these two types of networks. Our results include decomposing the edges into disjoint Hamiltonian cycles, a simplification of the calculation of the Eisenstein-Jacobi distance, a distribution of the distances between Eisenstein-Jacobi nodes, and shortest path routing algorithms. In particular, the known Gaussian routing algorithm is simplified.Index Terms-Interconnection network, Gaussian integers, Eisenstein-Jacobi integers, routing in networks, diameter of a network.

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Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors

Cited by 28 publications

References 22 publications

All-To-All Broadcast in Hexagonal Torus Networks On-Chip

All-To-All Broadcast in Hexagonal Torus Networks On-Chip

A distributed concurrent on-line test scheduling protocol for many-core NoC-based systems

The Topology of Gaussian and Eisenstein-Jacobi Interconnection Networks

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