Dependability Aspects Regarding the Cache Level of a Memory Hierarchy using Hamming Codes

Novac, Ovidiu Constantin; Vari-Kakas, St.; Novac, Mihaela Cornelia; Vladu, Ecaterina; Indrie, Liliana

doi:10.1007/978-90-481-9112-3_98

Cited by 2 publications

(1 citation statement)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Fig. 2 demonstrates the general organization of a fault tolerant cache memory [7], [8]. The fault tolerance is assumed to be implemented in the data area, based on information redundancy with the use of an error correcting code.…”

Section: Fault Tolerant Cache and Performance Metricsmentioning

confidence: 99%

Performance-Oriented Design of Fault Tolerant Cache Architectures

Novac¹,

Vari-Kakas²,

Novac³

et al. 2012

Proceedings of the 23rd International DAAAM Symposium 2012

View full text Add to dashboard Cite

In this paper, we present aspects regarding the possibility of maximizing the performance/cost ratio in the cache memory design. A cache is a component that improves performance by transparently storing data so that future requests for that data can be served faster. Caches provide for efficient read/write access to memory, and their reliability is essential to assure dependable computing. Usually the cache design goal is to find such an architecture that maximizes the hit ratio. This paper offers the designer a computer simulation based method, taking into account classical performance metrics and reliability aspects.

show abstract

Section: Fault Tolerant Cache and Performance Metricsmentioning

confidence: 99%

Performance-Oriented Design of Fault Tolerant Cache Architectures

Novac¹,

Vari-Kakas²,

Novac³

et al. 2012

Proceedings of the 23rd International DAAAM Symposium 2012

View full text Add to dashboard Cite

show abstract

Compact and High-Speed Hsiao-Based SEC-DED Codec for Cache Memory

Samanta

Kewat

2021

J CIRCUIT SYST COMP

View full text Add to dashboard Cite

Recently, there have been continuous rising interests of multi-bit error correction codes (ECCs) for protecting memory cells from soft errors which may also enhance the reliability of memory systems. The single error correction and double error detection (SEC-DED) codes are generally employed in many high-speed memory systems. In this paper, Hsiao-based SEC-DED codes are optimized based on two proposed optimization algorithms employed in parity check matrix and error correction logic. Theoretical area complexity of SEC-DED codecs require maximum 49.29%, 18.64% and 49.21% lesser compared to the Hsiao codes [M. Y. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBM J. Res. Dev. 14 (1970) 395–401], Reviriego et al. codes [P. Reviriego, S. Pontarelli, J. A. Maestro and M. Ottavi, A method to construct low delay single error correction codes for protecting data bits only, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 32 (2013) 479–483] and Liu et al. codes [S. Liu, P. Reviriego, L. Xiao and J. A. Maestro, A method to recover critical bits under a double error in SEC-DED protected memories, Microelectron. Reliab. 73 (2017) 92–96], respectively. Proposed codec is designed and implemented both in field programmable gate array (FPGA) and ASIC platforms. The synthesized SEC-DED codecs need 31.14% lesser LUTs than the original Hsiao code. Optimized codec is faster than the existing related codec without affecting its power consumption. These compact and faster SEC-DED codecs are employed in cache memory to enhance the reliability.

show abstract

Dependability Aspects Regarding the Cache Level of a Memory Hierarchy using Hamming Codes

Cited by 2 publications

References 1 publication

Performance-Oriented Design of Fault Tolerant Cache Architectures

Performance-Oriented Design of Fault Tolerant Cache Architectures

Compact and High-Speed Hsiao-Based SEC-DED Codec for Cache Memory

Contact Info

Product

Resources

About