Dependable system design with soft error mitigation techniques in SRAM based FPGAs

Nidhin, T. S.; Bhattacharyya, Anindya; Behera, R. P.; Jayanthi, T.; Velusamy, K.

doi:10.1109/ipact.2017.8244907

Cited by 6 publications

(3 citation statements)

References 9 publications

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“…Many researchers have proposed different techniques to manage soft errors in FPGAs. [10][11][12][13][14][15] Adewale Adetomi et al [10], designed ICAP Controller with a selective-area soft error Mitigation Engine. They tried to scan selective-area of the FPGA instead of entire device which saved them the time available for reconfiguration.…”

Section: Previous Related Workmentioning

confidence: 99%

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Design and Implementation of Reliable Encryption Algorithms through Soft Error Mitigation

S¹,

Dinesha²,

Shashikala³

et al. 2020

IJCNIS

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Designing a reliable system on reconfigurable devices has become a significant factor for implementing mission critical applications like communication protocols, automotive, nuclear reactor control, and remote applications. With the improvement in fabrication technology, logic density of the field programmable gate arrays has increased rapidly. Because of decrease in feature size, integrated circuits are becoming vulnerable to errors and also the ageing component results in run time faults. FPGAs when used in harsh conditions like high radiation and temperatures, there is a possibility of getting affected by transient faults or the soft errors. In digital communication, safety and confidentiality of data is achieved through a suitable encryption algorithm. Encryption is most important aspect when it comes to security. Reliable design techniques are very much necessary for maintaining the system's normal function. Many of the available techniques are based on redundancy logic causing area overhead for the design. Through this paper, an implementation is illustrated for managing soft errors or the single event upsets. Proposed methodology identifies and avoids the errors occurring at the logic resources where the encryption algorithms are mapped on the device. Thus encryption algorithms work normally without getting affected by the errors. During the simulation process, errors are injected at the configuration memory frames and monitored using a Single event-upset manager (SEM) controller. The proposed design is implemented on Zedboard using Xilinx Vivado 2017.4.

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Section: Previous Related Workmentioning

confidence: 99%

“…They also proposed hardware architecture with partial reconfiguration for the designed code. S. Nidhin et al [12] worked on error injection in the logic function modifying VHDL code. For analyzing the concept redundancy and duplication with compare were used.…”

Section: Previous Related Workmentioning

confidence: 99%

Design and Implementation of Reliable Encryption Algorithms through Soft Error Mitigation

S¹,

Dinesha²,

Shashikala³

et al. 2020

IJCNIS

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show abstract

“…If SEUs occur in LUT cells or in the cells that control the routing and selectors, it will cause circuit output errors (Morgan et al, 2005), as depicted in Figure 1. These errors have a permanent impact (Nidhin et al, 2017) because these upsets have been latched by the configuration cells. Therefore, certain measures must be taken to prevent the SEUs from affecting the applications and to repair errors.…”

Section: Introductionmentioning

confidence: 99%

Soft error mitigation and recovery of SRAM-based FPGAs using brain-inspired hybrid-grained scrubbing mechanism

Xie,

Qiao,

Xie

et al. 2023

Front. Comput. Neurosci.

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Soft error has increasingly become a critical concern for SRAM-based field programmable gate arrays (FPGAs), which could corrupt the configuration memory that stores configuration data describing the custom-designed circuit architecture. To mitigate this kind of error, this study proposes a brain-inspired hybrid-grained scrubbing mechanism consisting of fine-grained and coarse-grained scrubbing to mitigate and repair the errors as quickly as possible after an SEU occurrence. Inspired by the human brain's ability to filter out redundant and irrelevant information, we propose a mechanism that can mask invalid position information when errors occur. Compared with the scrubbing of full configuration memory, this mechanism can achieve precise error location and recovery utilizing targeted scrubbing of specific frames or modules. The effectiveness is evaluated by executing fault injection campaigns on the International Symposium on Circuits and Systems 1989 (ISCAS89) benchmark circuits and fault tolerant fast Fourier transform (FT-FFT) circuit. If upsets are detected, they will be repaired with fine-grained or coarse-grained scrubbing depending on their location. The experiment results show that this mechanism can effectively mitigate and repair single-bit upsets (SBUs) and double-bit upsets (DBUs). In addition, the mechanism is proven to be superior in error recovery time and hardware overhead compared to counterpart approaches.

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Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-Based Experimental Robot Controller

Podivinsky

Lojda

Cekan

et al. 2018

2018 21st Euromicro Conference on Digital System Design (DSD)

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Dependable system design with soft error mitigation techniques in SRAM based FPGAs

Cited by 6 publications

References 9 publications

Design and Implementation of Reliable Encryption Algorithms through Soft Error Mitigation

Design and Implementation of Reliable Encryption Algorithms through Soft Error Mitigation

Soft error mitigation and recovery of SRAM-based FPGAs using brain-inspired hybrid-grained scrubbing mechanism

Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-Based Experimental Robot Controller

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