Deposition Temperature and Thermal Annealing Effects on the Electrical Characteristics of Atomic Layer Deposited Al2O3 Films on Silicon

Abstract

Atomic layer deposition (ALD) of Al2O3 is of interest for a wide range of micronanoelectronic applications, where the electrical properties of the deposited layers can be strongly affected by deposition conditions and post-deposition treatments. In this work, a mercury-probe capacitance-voltage characterization is carried out on Al2O3 films deposited on silicon by ALD at different temperatures and subjected to various thermal treatments in N2 ambient. Effective positive charges located at the semiconductor/dielectric interface are encountered for the films deposited at the lowest temperature (100ºC). Positive Vfb shifts are always registered after the different thermal annealing conditions studied; however, the impact of the thermal treatments is found to be different depending on the deposition temperature. A significant negative charges build-up is observed after a 30 minutes anneal at 450ºC, where improved surface passivation properties are achieved. Interestingly, the hysteresis, as well as the Vfb shifts, clearly diminish for higher deposition temperatures or after a thermal anneal. However, the highest temperature treatments (800ºC) result in significant interface states generation. Finally, exploratory experiments about the stability of the Al2O3 layers under UV-light irradiation (in the 200 nm-300 nm wavelengths range) show that this can be responsible for a significant degradation of their electrical characteristics.

Influence of deposition temperature of thermal ALD deposited Al2O3 films on silicon surface passivation

“…The Q F of as-deposited films is positive which are listed in Table III. Rafi et al 36 also observed positive fixed charges in the Al 2 O 3 films deposited at 100 Table III) which confirms that there is an activation of negative fixed charges in these films. The density and polarity of fixed charges are related to the deposition process of oxide films and is associated with local non-stoichiometry or structural defects.…”

“…All these results demonstrate that deposition temperature and post-deposition annealing both play important role for surface passivation. [33][34][35][36][37][38] ) as a function of t anl of as-deposited and annealed (t anl = 90 s, 105 s, 120 s) samples of S 100 , S 200 and S 300 . The minimum SRV value (∼7 cm/s) obtained using low thermal budget RTP process is quite comparable to the values realized with high thermal budget.…”

Influence of the SiO2 interlayer thickness on the density and polarity of charges in Si/SiO2/Al2O3 stacks as studied by optical second-harmonic generation

“…To our knowledge it was the first time that the role of the SiO 2 interlayer on the built-in charge density was clearly established even though it has been often speculated that the presence of negative charges in Al 2 O 3 thin films on silicon is associated with the presence of interfacial SiO 2 between the silicon and the Al 2 O 3 . [10][11][12][13] In our previous work we did, however, not conclusively establish the origin and physical location of the charges in the stacks. Furthermore, the SiO 2 interlayers (1-13 nm) were prepared solely by atomic layer deposition (ALD) and only n-type silicon wafers were used.…”

Effective lifetimes exceeding 300 μs in gettered p-type epitaxial kerfless silicon for photovoltaics

“…26,30 The model assumes a 20 nm passivation layer with an index of refraction of 1.63. 31 To minimize noise in the data, 50 measurements are averaged for high lifetime (>100 ls) samples. Error bounds for lifetime are 610%.…”