Depth dependent carrier density profile by scanning capacitance microscopy

Abstract

Two dimensional dopant and carrier profiles obtained by scanning capacitance microscopy on an actively biased cross-sectioned metal-oxide-semiconductor field-effect transistor The depth dependent carrier density was measured on an arsenic implanted silicon sample using scanning capacitance microscopy ͑SCM͒. The capacitance versus voltage scan was performed by applying dc biases with a dither ac signal. A strong dc bias dependence was observed at the interface of an abrupt junction between n ϩ and p. The bias dependent SCM images show good agreement with quasi-three dimensional simulations, suggesting that they can be used to map a device structure.

Charge trap dynamics in a SiO2 layer on Si by scanning capacitance microscopy

“…1͑D͔͒. Since the image change was not apparent at zero bias, the dC/dV images were taken at the bias of Ϫ1.1 V. As reported earlier, 14 the unimplanted area shows a dark center with a brighter edge due to the accumulated hole carriers in the unimplanted region, even without trapped charge. The dark center now changes to bright with trapped holes.…”

“…As an application, Barret and Quate were able to image the trapped charge in a nitrideoxide-semiconductor structure ͑NOS͒ with a SCM and proposed to use the structure for data storage. 11 As reported earlier, 14 the carrier density at a specific depth could be mapped from the measured capacitance by applying a proper bias voltage. As the depletion width is a function of dopant density and the bias applied to the tip as an effective gate, SCM images show the dopant profile from the interface region ͑between the silicon dioxide and the silicon͒ to a deeper region into the silicon by increasing the bias voltage.…”

Local electronic properties of AlGaN/GaN heterostructures probed by scanning capacitance microscopy

“…This technique has been used extensively to perform dopant profiling in Si device structures, [11][12][13] and more recently to characterize local surface electronic structure in nGaN epitaxial layers. 14 By measuring capacitance properties between a conducting proximal probe tip and the sample at a fixed tip-sample bias voltage, lateral variations in mobile carrier distributions can be observed at length scales ranging from <0.1 µm to several µm.…”

Scanning capacitance spectroscopy on n+-p asymmetrical junctions in multicrystalline Si solar cells

“…However, because the value of V s yielding a flat-band condition is, in general, different between the p-and n-regions of the device, and because the capacitance response near the junction is complicated by the low carrier density in the junction depletion region, the apparent EJ location, as determined by dC/dV ¼ 0, depends on the value of V s and has an error of 6W, where W is the junction depletion width. [1][2][3][4] For a narrow junction in a field-effect transistor, W is similar to the SCM probe size, a few tens of nm. However, for low-doped n þ -p junctions, such as those in crystalline Si (c-Si) solar cells, W is typically a few hundred nm, and a more complete understanding of the SCM signal in the vicinity of the junction is desirable for characterizing these devices.…”