Depth-Reliability-Based Stereo-Matching Algorithm and Its VLSI Architecture Design

Abstract

A low-complexity depth-reliability-based stereomatching algorithm and an efficient scanline memory-merging implementation scheme are proposed in this paper. The developed algorithm analyzes the accuracy of disparity results by using simple local window-based methods and preserves reliable information only. A bidirectional depth propagation flow is then adopted to fill the unreliable segments by using reliable information. Moreover, a set of predefined function-specific reliability variables are extracted to further improve depth quality in the occluded and smooth regions, which can reduce 39% bad pixels obtained by applying the basic 7 × 7 window-based matching. The proposed scanline memory-merging scheme along with data prefetching can lead to 32.7% savings on the scanline memory area and relax the requirements of external frame buffer size and bandwidth. Experimental results show that the implemented stereo-matching hardware has a gate count of 223 k including the scanline memory, and can achieve up to 70 frames/s for 480 × 540 resolution (2 × 2 downsampling of FullHD side-by-side 3-D format) with 56 disparity levels.Index Terms-Reliability-based computation, stereo-matching, window-based sum of absolute differences (SAD) architecture.

Model Based Design of a Real Time FPGA-Based Lens Undistortion and Image Rectification Algorithm for Stereo Imaging

“…The accomplishment of applying these algorithms to hardware is highlighted by the historic difficulty in working with FPGAs and HDL. Early researchers simply hand-coded the necessary HDL which is often time consuming and tedious to debug [15]. Other researchers have proposed various solutions to speed up the development process to still benefit from the speed and flexibility of FPGAs.…”

“…Therefore the mapping must be split up to the surrounding 4 pixels via a process known as bilinear interpolation. The interpolation is shown in (14)(15)(16)(17) and shows how a point (u, v) is represented by the surrounding pixels G 0 , G 1 , G 2 , G 3 utilizing deltaU and deltaV which describe the location of the sub-pixel in relation to the nearest pixels.…”

All-hardware acceleration for binocular vision 3D positioning system

“…In recent years, some FPGA-based hardware acceleration implementation solutions have been released. [5][6][7][8][9] They all use FPGA+CPU to accelerate the binocular vision system. Compared with the traditional CPU or GPU implementation, the speed and power consumption are greatly improved.…”