Deriving efficient cache coherence protocols through refinement

Nalumasu, Ratan; Gopalakrishnan, Ganesh

doi:10.1007/3-540-64359-1_748

Cited by 5 publications

(3 citation statements)

References 13 publications

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“…All experiments were performed using an executiondriven simulation of the Avalanche architecture [3,14]. Our simulation environment includes detailed simulation modules for a first level cache, system bus, memory controller, network interconnect, and DSM engine.…”

Section: Methodsmentioning

confidence: 99%

Design alternatives for shared memory multiprocessors

Carter

Kuo²,

Kuramkote³

et al.

Proceedings. Fifth International Conference on High Performance Computing (Cat. No. 98EX238)

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In this paper, we consider the design alternatives available for building the next generation DSM machine (e.g., the choice of memory architecture, network technology, and amount and location of per-node remote data cache). To investigate this design space, we have simulated five applications on a wide variety of possible DSM architectures that employ significantly different caching techniques. We also examine the impact of using a special-purpose system interconnect designed specifically to support low latency DSM operation versus using a powerful off the shelf system interconnect. We found that two architectures have the best combination of good average performance and reasonable worst case performance: CC-NUMA employing a moderate-sized DRAM remote access cache (RAC) and a hybrid CC-NUMA/S-COMA architecture called AS-COMA or adaptive S-COMA. Both pure CC-NUMA and pure S-COMA have serious performance problems for some applications, while CC-NUMA employing an SRAM RAC does not perform as well as the two architectures that employ larger DRAM caches. The paper concludes with several recommendations to designers of next-generation DSM machines, complete with a discussion of the issues that led to each recommendation so that designers can decide which ones are relevant to them given changes in technology and corporate priorities.

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Section: Methodsmentioning

confidence: 99%

Design alternatives for shared memory multiprocessors

Carter

Kuo²,

Kuramkote³

et al.

Proceedings. Fifth International Conference on High Performance Computing (Cat. No. 98EX238)

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“…We already have numerous examples of manually optimized MPI programs, and plan to apply our techniques to show how these examples can be re-derived using our transformation system. Our past experience in cache coherence protocol synthesis [22] has given us some background experience.…”

Section: High Level Transformationsmentioning

confidence: 99%

Toward reliable and efficient message passing software through formal analysis

Gopalakrishnan

Kirby

2006

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

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The quest for high performance drives parallel scientific computing software design. Well over 60% of the high-performance computing (HPC) community writes programs using the MPI library; to gain performance, they are known to perform many manual optimizations. Even tools that accept high level descriptions often generate MPI code, due to its eminent portability. However, since the overall performance of a program does not usually port (due to variations in the target architecture, cluster size, etc.), manual changes to the code are inevitable in today's approaches to MPI programming and optimization. This, together with the vastness and evolving nature of the MPI standard, and the innate complexity of concurrent programming introduces costly bugs.Our research addresses these challenges through specific efforts in the following broad areas: (i) high level expression of the parallel algorithm and compilation thereof into optimized MPI programs, (ii) optimizations of user-written detailed MPI programs through localized transformations such as barrier removal, (iii) formal modeling of complex communication standards, such as the MPI-2 standard and a facility for answering putative queries (this need arises when standard documents are impossibly difficult to manually study in order to answer questions that are not explicitly addressed in the standard), (iv) formal modeling of new (and hence relatively less well understood) features of communication libraries, such as the one-sided communication facility of MPI-2, and (v) formal modeling of intricate control algorithms in these libraries such as the progress engine for TCP and/or shared memory in MPICH2 (a formal model can explicate commonalities, help formally verify, as well as help create better future implementations). Our research gains focus through * Supported in part by NSF award CNS-0509379 numerous collaborations.

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“…Notions similar to flushing are also used for correctness criteria in other domains, such as cache-coherence protocol verification (e.g. [PD96,SA97,NG98]).…”

Section: Flushingmentioning

confidence: 99%

A Framework for Microprocessor Correctness Statements

Aagaard

Cook²,

Day³

et al. 2001

Lecture Notes in Computer Science

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Most verifications of out-of-order microprocessors compare state-machine-based implementations and specifications, where the specification is based on the instruction-set architecture. The different efforts use a variety of correctness statements, implementations, and verification approaches. We present a framework for classifying correctness statements about safety that is independent of implementation representation and verification approach. We characterize the relationships between the different statements and illustrate how existing and classical approaches fit within this framework.

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Deriving efficient cache coherence protocols through refinement

Cited by 5 publications

References 13 publications

Design alternatives for shared memory multiprocessors

Design alternatives for shared memory multiprocessors

Toward reliable and efficient message passing software through formal analysis

A Framework for Microprocessor Correctness Statements

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