Design an Improved Structure for 10-Bit Pipeline Analog to Digital Converter Based on 0.18µm CMOS Technology

Abstract

This paper proposed a novel structure of a 10-bit, 400MS/s pipelined analog to digital convertor using 0.18 µm TSMC technology. In this paper, two stages are used to converter design and a new method is proposed to increase the speed of the pipeline analog to digital convertor. For this purpose, the amplifier is not used at the first stage and the buffer is used for data transfer to the second stage, in the second stage an amplifier circuit with accurate gain of 8 that is open loop with a new structure was used to speed up, also the design is such that the first 4 bits are extracted simultaneously with sampling. On the other hand, in this structure, since in the first stage the information is not amplified and transferred to the second stage, the accuracy of the comparator circuit should be high, therefore a new structure is proposed to design a comparator circuit that can detect unwanted offsets and eliminate them without delay, and thus can detect the smallest differences in input voltage. The proposed analog to digital convertor was designed with a resolution of 10 bits and a speed of 400MS/s, with the total power consumption 74.3mW using power supply of 1.8v.

The 1.5 bit-per-stage 10-bit pipelined CMOS A/D converter for CMOS image sensor

“…Thus, those comparators offer amplification of the differential input voltage thanks to the preamplifier, which forms the first stage of each comparator. A regenerate latch works on the regeneration depending on the voltage difference between the two inputs [12], [13]. The last stage of our comparator design is the output buffer or post-amplifier, which has the purpose of converting the output of the decision circuit into a logic signal [14].…”

An Enhanced Strong ARM Comparator Circuit for Analog to Digital Converter Architectures

“…Ramamurthy et al proposed a digital calibration technique to enhance the signal to noise distortion ratio almost to 20dB [9]. The authors in [10] present a novel pipelined ADC architecture in 180nm CMOS process. The methodology is based on by inserting a buffer circuit in second stage due to which offset voltage is eliminated without any delay.…”