Design analysis of a low-power, high-speed 8 T SRAM cell using dual-threshold CNTFETs

Abstract

Recently, carbon nanotube field-effect transistors (CNTFETs) have garnered significant attention from VLSI engineers due to their exceptional electrical properties. This paper proposes a novel high-speed, low-power eight-transistor (8 T) static random-access memory (SRAM) cell based on 32-nm CNTFET technology. The SRAM cell was simulated using the HSPICE tool with a VDD of 0.9 V. The high-speed and low-power characteristics of the SRAM design are attributed to the high subthreshold slope and high carrier mobility of metal-oxide-semiconductor field-effect transistor (MOSFET)-like CNTFETs utilized in the simulations. The implementation of dual threshold transistors, coupled with a transmission gate for bitline access, contributes to the enhanced performance. Key performance metrics such as noise margins, power consumption, delay, and SRAM electrical quality metric (SEQM) of the proposed SRAM have been evaluated and compared with existing CNTFET-based SRAM designs. The proposed cell demonstrates reductions of 73.73%, 43.18%, and 58.70% in read power, write power, and hold power, respectively, compared to the lowest respective power values of other examined SRAM designs. The proposed SRAM ranks second, third, and second in write static noise margin (WSNM), hold static noise margin (HSNM), and read static noise margin (RSNM), respectively, among other designs. Additionally, the proposed SRAM exhibits the least sensitivity to parametric variations compared to other designs. The SEQM, which provides a comprehensive assessment of access times, noise margins, and power usage for the SRAM cell, has been calculated. The SEQM of the proposed SRAM is 10.6, 1.89, 13.15, and 1.82 times higher than that of C6T, BLP8T, Mani’s 10 T, and LP8T, respectively.