Design and analysis of 12.8 Gb/s single-ended signaling for memory interface

Beyene, W.T.; Amirkhany, Amir; Madden, Chris; Lan, Hai; Yang, Liu; Kaviani, K.; Mukherjee, S.; Secker, D.; Schmitt, R.

doi:10.1109/epeps.2011.6100208

Cited by 2 publications

(2 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…These include cross talk, simultaneous switching noise (SSN), inter-symbol interference (ISI), supply noise and its impact on internal clocking circuit jitter, etc. A number of key techniques have been applied to address some of these concerns, including advanced equalizations, precise on-die termination (ODT) calibration, reference voltage supply noise tracking, and novel data bit encoding (DBE) [3]. One important aspect of the PI challenges yet to be investigated is the on-chip power supply noise induced jitter (PSIJ).…”

Section: Introductionmentioning

confidence: 99%

Modeling and measurement of supply noise induced jitter in a 12.8Gbps single-ended memory interface

Lan

Han

Schmitt

2012

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems

View full text Add to dashboard Cite

Analyzing power supply noise characteristics and predicting its jitter impact is critical in designing the 12.8Gbps single-ended memory interface achieving better than 5mW/Gbps energy efficiency. The clocking circuit jitter performance is characterized by jitter sensitivity. The power supply noise induced jitter (PSIJ) is derived by combining the noise spectrum and sensitivity profile. The final PSIJ prediction matches closely with the on-chip measurement result.

show abstract

Section: Introductionmentioning

confidence: 99%

Modeling and measurement of supply noise induced jitter in a 12.8Gbps single-ended memory interface

Lan

Han

Schmitt

2012

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems

View full text Add to dashboard Cite

show abstract

“…To properly characterize the PSIJ, PSIJ analysis methodology [22][23] [24] [25] has been proposed and applied to multi-gigabit I/O interface design. The key concept of power supply induced jitter sensitivity (PSIJS) has been proposed and applied to PSIJ analysis.…”

Section: Ddr Controller and Design Challengesmentioning

confidence: 99%

Reduction of Power Supply Induced Jitter with Applications to DDR Controllers

Wang¹

View full text Add to dashboard Cite

It is desirable to improve the tradeoff between the power supply induced jitter (PSIJ) performance and the cost for the clock distribution circuit in a double data rate (DDR) controller. This thesis proposes the following techniques to achieve the goal: The static phase offset (SPO) is the dominant mechanism causing reference spurs in the spectrum of the multiplying delay-locked loop (MDLL) output. With a high-gain stage inserted between the phase detector/phase frequency detector and the charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. The

show abstract

Design and analysis of 12.8 Gb/s single-ended signaling for memory interface

Cited by 2 publications

References 8 publications

Modeling and measurement of supply noise induced jitter in a 12.8Gbps single-ended memory interface

Modeling and measurement of supply noise induced jitter in a 12.8Gbps single-ended memory interface

Reduction of Power Supply Induced Jitter with Applications to DDR Controllers

Contact Info

Product

Resources

About