Design and Analysis of 16-bit RISC Processor

Bhagat, Shraddha M.; Bhandari, Sheetal U.

doi:10.1109/iccubea.2018.8697859

Cited by 16 publications

(3 citation statements)

References 2 publications

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“…Furthermore, they developed a simulator where users can type their assembly instructions and examine the code step by step. On the other hand, Bhagat & Bhandari (2018) did not only design a 16-bit RISC processor but also, verified their design by using Verilog HDL. Similar to Bhagat & Bhandari (2018) , Angelov & Lindenstruth (2009) also used Von Neumann architecture.…”

Section: Related Workmentioning

confidence: 99%

“…On the other hand, Bhagat & Bhandari (2018) did not only design a 16-bit RISC processor but also, verified their design by using Verilog HDL. Similar to Bhagat & Bhandari (2018) , Angelov & Lindenstruth (2009) also used Von Neumann architecture. However, their design is limited to support 15 different instructions to make the processor simpler and easier to design.…”

Section: Related Workmentioning

confidence: 99%

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Teaching computer architecture by designing and simulating processors from their bits and bytes

Doğan,

Öztoprak,

Tolun

2024

PeerJ Computer Science

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Teaching computer architecture (Comp-Arch) courses in undergraduate curricula is becoming more of a challenge as most students prefer software-oriented courses. In some computer science/engineering departments, Comp-Arch courses are offered without the lab component due to resource constraints and differing pedagogical priorities. This article demonstrates how students working in teams are motivated to study the Comp-Arch course and how instructors can increase student motivation and knowledge by taking advantage of hands-on practices. The teams are asked to design and implement a 16-bit MIPS-like processor with constraints as a specific instruction set, and limited data and instruction memory. Student projects include following three phases, namely, design, desktop simulator implementation, and verification using hardware description language (HDL). In the design phase, teams develop their Comp-Arch to implement specified instructions. A range of designs resulted, e.g., (a) a processor with extensive user-defined instructions resulting in longer cycle times (b) a processor with a minimal instruction set but with a faster clock cycle time. Next, teams developed a desktop simulator in any programming language to execute instructions on the architecture. Finally, students engage in Verilog Hardware Description Language (HDL) projects to simulate and verify the data-path designed during the initial phase. Student feedback and their current understanding of the project were collected through a questionnaire featuring varying Likert scale questions, some with a ten-point scale, and others with a five-point scale. Results of the survey show that the hands-on approach increases students’ motivation and knowledge in the Comp-Arch course, which is centered around computer system design principles. This approach can also be effectively extended to related courses, such as Microprocessor Design, which delves into the intricacies of creating and implementing microprocessors or central processing units (CPUs) at the hardware level. Furthermore, the present study demonstrates that interactions, specifically through peer reviews and public presentations, between students in each phase increases their knowledge and perspective on designing custom processors.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Teaching computer architecture by designing and simulating processors from their bits and bytes

Doğan,

Öztoprak,

Tolun

2024

PeerJ Computer Science

View full text Add to dashboard Cite

show abstract

“…Neumann architecture supporting load/store instructions on FPGA Spartan 6, proved it has area utilization very less is kept forward in 2018. Digital modulation techniques [5] like binary amplitude-shift keying (BASK), binary frequency-shift keying (BFSK), binary phase-shift keying (BPSK), and quadrature phase shift keying (QPSK) are simulated successfully in the Xilinx environment with a 32-bit serial data transmission with self-adjustable carrier frequency and bit duration length.…”

Section: Introductionmentioning

confidence: 99%

A novel reduced instruction set computer-communication processor design using field programmable gate array

Prathap¹,

Ramesh

2023

IJRES

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In this paper, a novel reduced instruction set computer (RISC)- communication processor (RCP) has been designed with 32-bit operations which access 64-bit instruction format and implemented using field programmable gate array (FPGA). The design of the RISC processor is facilitated with communication operations like basic signals sine, cosine, and square, and modulation schemes like amplitude modulation, amplitude shift keying, analog, and digital quadrature amplitude modulation. Additionally, application-oriented operations like a traffic light, digital clock, and linear feedback shift register are included in the design. The pipeline mechanism is incorporated in the design to enhance the performance characteristics of the processor, hence allowing the execution of the instructions more effectively. Also, the design is implemented with Xilinx Virtex 7 family FPGA. The device utilization analysis of the proposed FPGA along with different FPGA families is evaluated and compared.

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Design and Implementation of 16-Bit Optimized RISC Processor with Novel Pipelining

Soni

Sarkar

Mathew

et al. 2023

Lecture Notes in Electrical Engineering

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Design and Analysis of 16-bit RISC Processor

Cited by 16 publications

References 2 publications

Teaching computer architecture by designing and simulating processors from their bits and bytes

Teaching computer architecture by designing and simulating processors from their bits and bytes

A novel reduced instruction set computer-communication processor design using field programmable gate array

Design and Implementation of 16-Bit Optimized RISC Processor with Novel Pipelining

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