Design and Analysis of a Low Power Bootstrapped Cmos Circuit

Abstract

This paper describes bootstrapped circuit operated at low voltage. First I have described bootstrapped driver circuit that operated at ultra low supply voltage. Bootstrapping is a technique that improves the driving ability of digital circuit that operated on very low voltage. In this paper I have proposed bootstrapped driver circuit using CADENCE virtuoso at 180nm as well as 90nm and comparison of both circuit are mentioned and also layout of proposed bootstrapped driver circuit is also shown. The proposed bootstrapped driver circuit minimizes area overhead as compared to conventional bootstrapped driver circuit. Proposed driver circuit uses less number of transistors as compared to conventional driver circuit. Conventional bootstrapped driver circuit operated at 1v to 1.5v, if we try to reduce that supply voltage for low power application then actual working of driver circuit get disturbed at 180nm. The circuit which I have proposed at 180nm takes minimum supply voltage of 0.8v and proposed driver circuit at 90nm take minimum supply voltage of 0.3v. Final output voltage of bootstrapped driver circuit will be boosted output that is above VDD and below GND. Both proposed bootstrapped driver circuit give low power dissipation and less leakage current and also less delay as compared to conventional bootstrapped driver circuit. Proposed bootstrapped driver circuit offers 94.93% improvement in power dissipation.