Design and analysis of a K-band low-phase-noise phase-locked loop with subharmonically injection-locked technique

Abstract

In this paper, we present design and analysis of a K-band (18 to 26.5 GHz) low-phase-noise phase-locked loop (PLL) with the subharmonically injection-locked (SIL) technique. The phase noise of the PLL with subharmonic injection is investigated, and a modified phase noise model of the PLL with SIL technique is proposed. The theoretical calculations agree with the experimental results. Moreover, the phase noise of the PLL can be improved with the subharmonic injection. To achieve K-band operation with low dc power consumption, a divide-by-3 injection-locked frequency divider (ILFD) is used as a frequency prescaler. The measured phase noise of the PLL without injection is -110 dBc/Hz at 1 MHz offset at the operation frequency of 23.08 GHz. With the subharmonic injection, the measured phase noises at 1 MHz offset are -127, -127, and -119 dBc/Hz for the subharmonic injection number NINJ = 2, 3, and 4, respectively. Moreover, the performance of the proposed PLL with and without SIL technique can be compared with the reported advanced CMOS PLLs.

A low phase noise and frequency agility synthesizer for millimeter-wave transceiver

“…[2] have the better phase noise and spurious performances, but its output frequency is lower and the frequency-hopping time is slower Yang et al . [9] used the architecture of PLL with a VCO, and did not consider frequency agility characteristics Yeh and Chang [10] designed and analyzed a K-band low phase noise PLL with the sub-harmonically injection-locked technique, but it cannot improve the loop lock time. The MMW PLL synthesizer employing a wide-locking range is designed by the injection-locked frequency divider in [11, 12], but the performance is not better than this work.…”