Design and Analysis of Braun Multiplier Using CMOS/GDI Technique for Signal Processing

Abstract

Efficient arithmetic circuits are needed for cost effective and computation intense signal processing applications. Electronic appliances such as pagers, notebook computers and laptops demands high reliable and portable circuits. With the advent of high performance chips, power dissipation has gained its importance for efficient chip design. The need to explore efficient design techniques has increased to achieve high throughput and reduced power dissipation. Addition is an obligatory and crucial arithmetic operation used in application specific and general purpose systems. This paper discusses the design of efficient adder and its implementation in Braun multiplier using different logic styles like Gate Diffusion Input (GDI) logic and Complementary Metal Oxide Semiconductor (CMOS). The design is implemented in Cadence Virtuoso tool for 45 nm technological node. The GDI logic style reduces the delay of Braun multiplier by 42.38% with power optimization compared with CMOS logic style.