Design and Analysis of Dual-Rail Circuits for Security Applications

Sokolov, Danil; Murphy, Julian P.; Bystrov, A.; Yakovlev, Alex

doi:10.1109/tc.2005.61

Cited by 115 publications

(53 citation statements)

References 15 publications

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“…For example, the multi-round power analysis attack is built to breach the countermeasures that are stratified by block cipher algorithm [31]. On the other side, several countermeasures intended to beat off the power analysis attacks over AES such as random masking [32] and hardware balancing [33]. Different techniques have different characteristics and some known with their high cost in different terms such as hardware balancing techniques.…”

Section: Side Channel Attacks: Differential Power Analysis Attack (Dpmentioning

confidence: 99%

Security and Privacy Challenges in Cyber-Physical Systems

Aldosari¹

2017

JIS

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Cyber-Physical Systems, or Smart-Embedded Systems, are co-engineered for the integration of physical, computational and networking resources. These resources are used to develop an efficient base for enhancing the quality of services in all areas of life and achieving a classier lifestyle in terms of a required service's functionality and timing. Cyber-Physical Systems (CPSs) complement the need to have smart products (e.g., homes, hospitals, airports, cities). In other words, regulate the three kinds of resources available: physical, computational, and networking. This regulation supports communication and interaction between the human word and digital word to find the required intelligence in all scopes of life, including Telecommunication, Power Generation and Distribution, and Manufacturing. Data Security is among the most important issues to be considered in recent technologies. Because Cyber-Physical Systems consist of interacting complex components and middle-ware, they face real challenges in being secure against cyber-attacks while functioning efficiently and without affecting or degrading their performance. This study gives a detailed description of CPSs, their challenges (including cyber-security attacks), characteristics, and related technologies. We also focus on the tradeoff between security and performance in CPS, and we present the most common Side Channel Attacks on the implementations of cryptographic algorithms (symmetric: AES and asymmetric: RSA) with the countermeasures against these attacks.

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Section: Side Channel Attacks: Differential Power Analysis Attack (Dpmentioning

confidence: 99%

Security and Privacy Challenges in Cyber-Physical Systems

Aldosari¹

2017

JIS

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“…Masking and randomized masking (Wang and Ha, 2013) is common method to prevent DPA. Balanced Load Dual Rail CMOS (Sokolov et al, 2005;Batina et al, 2005;Kulikowski et al, 2005;Tiri and Verbauwhede, 2005;Bucci et al, 2005), where gates are balanced so that load switching capacitance is same. This has significant area and power overhead.…”

Section: Related Workmentioning

confidence: 99%

A Defense Mechanism for Differential Power Analysis Attack in AES

Rajaram¹,

Vijaya²

2015

Journal of Computer Science

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Abstract:In modern wireless communication world, the security of data transfer has been the most challenging task. In embedded system, AES is the most extensively used cryptographic algorithm in practice. But its functionality has been disrupted by the DPA attack. There have been several countermeasures to tackle those attacks, but this study proposes variably a new measure to defend this DPA attack. DPA attack is possible due to the power fluctuation happening due to sequential circuit clocking during the process of substitute byte in AES encryption in the first round and last round. Hence to prevent this, the power variation is maintained at a constant pace throughout the data processing. This is achieved by incorporating a combinational logic design instead of a sequential logic circuit in AES. The proposed design is implemented in Vertex III FPGA device and found even after 17230 power traces the secret key is not disclosed as the power fluctuations is completely random. The power consumption when experimented by micro wind software proves to be constant and the same power (almost) is obtained while implementing it hardware and no chance of identifying the instant of data processing is achieved.

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“…Differential logic on the other hand attempts to make the resulting power consumption constant [5] [6]. The most prominent of these technologies is Wave Dynamic Differential Logic (WDDL, [6]).…”

Section: Background: Side-channel Resistant Logicmentioning

confidence: 99%

Secure FPGA circuits using controlled placement and routing

Schaumont

2007

Proceedings of the 5th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis

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In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an existing circuit within the same FPGA fabric. We have solved this problem in a way that still enables us to modify the logic function of the copied sub-module. Our technique has important applications in the design of side-channel resistant implementations in FPGA. Starting from an existing single-ended design, we are able to create a complementary circuit. The resulting overall circuit strongly reduces the power-consumption-dependent information leaks. We show that the direct mapping of a secure ASIC circuit-style in an FPGA does not preserve the same level of security, unless our symmetrical routing technique is employed. We demonstrate our approach on an FPGA prototype of a cryptographic design, and show through power-measurements followed by side-channel power analysis that secure logic implemented with our approach is resistant whereas non-routing-aware directly mapped circuits can be successfully attacked.

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Design and Analysis of Dual-Rail Circuits for Security Applications

Cited by 115 publications

References 15 publications

Security and Privacy Challenges in Cyber-Physical Systems

Security and Privacy Challenges in Cyber-Physical Systems

A Defense Mechanism for Differential Power Analysis Attack in AES

Secure FPGA circuits using controlled placement and routing

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