Design and analysis of efficient synthesis algorithms for EDAC functions in FPGAs

Abstract

Error Detection and Correction (EDAC) functions have been widely used for protecting memories from single event upsets (SEU), which occur in environments with high levels of radiation or in deep submicron manufacturing technologies. This paper presents three novel synthesis algorithms that obtain areaefficient implementations for a given EDAC function, with the ultimate aim of reducing the number of sensitive configuration bits in SRAM-based Field-Programmable Gate Arrays (FPGAs). Having less sensitive bits results in a lower chance of suffering a SEU in the EDAC circuitry, thus improving the overall reliability of the whole system. Besides minimizing area, the proposed algorithms also focus on improving other figures of merit like circuit speed and power consumption. The executed benchmarks show that, when compared to other modern synthesis tools, the proposed algorithms can reduce the number of utilized look-up tables (LUTs) up to a 34.48%. Such large reductions in area usage ultimately result in reliability improvements over 10% for the implemented EDAC cores, measured as MTBF (Mean Time Between Failures). On the other hand, maximum path delays and power consumptions can be reduced up to a 17.72% and 34.37% respectively on the placed and routed designs.Index Terms-field programmable gate arrays (FPGA), synthesis tools, efficient synthesis, error detection and correction (EDAC), single event upsets (SEU)

Spider monkey optimization–based high‐level synthesis in VLSI circuits for runtime adaptability

“…Although the optimization techniques were introduced, optimal FU according to PVT variations was not selected. Three new synthesis algorithms were designed in the work of Colodro‐Conde and Toledo‐Moreo 20 for area‐efficient implementations with Error Detection And Correction (EDAC) function to lessen number of sensitive configuration bits in SRAM‐based FPGAs. However, the error rate was not minimized using synthesis algorithms.…”

Fault‐tolerant method for anti‐SEU of embedded system based on dual‐core processor

“…Error detection and correction (EDAC) [8–10] circuit is also an important anti‐SEUs method. It can detect and correct SEUs error which mainly use anti‐SEUs of the cache, memory, and BRAM.…”

Contribuciones a tecnología y técnicas para astronomía terrestre y espacial síntesis de codecs EDAC, AOLI y COELI

“…The results of the initial studies that have just been described motivated the development of new synthesis algorithms more sophisticated than MISO that could process several outputs in a joint manner, that is, following a Many-Input, Multiple-Output (MIMO) approach. The resulting algorithms, named FS-EDAC (Full Search EDAC) and G-EDAC (Greedy EDAC), represent the main contributions of the present dissertation in the field of FPGA synthesis algorithms specialized in EDAC codecs [64].…”