Design and analysis of linear feedback shift register(LFSR) using gate diffusion input(GDI) technique

Sharma, Rishabh; Singh, Batwinder

doi:10.1109/wecon.2016.7993424

Cited by 10 publications

(3 citation statements)

References 9 publications

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“…This method is proposed to reduce the count of switching activities at the input sides of the circuit that is under test. As the power dissipation during testing mode is high compared to normal mode of operation, low power LFSR using gate diffusion input (GDI) technique is designed in [14]. Various combinational synchronous functions could be implemented using this technique with no more than two transistors.…”

Section: A Power Optimization Techniquesmentioning

confidence: 99%

Low Power Implementation of Linear Feedback Shift Registers

Jayasanthi¹,

AK²

2019

IJRTE

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This paper describes low power design and implementation of Linear Feedback Shift Register (LFSR). The easiness in implementation and simple operation of Linear Feedback Shift Register have made it fit into a wide range of digital systems design. Since random pattern generation, data encryption and decryption play a major role in communication systems, the LFSR comes into view for developing the patterns for these applications. As the need increases day after day, simple and high-performance design of LFSR is required. As power consumption of the device being an important factor in the VLSI circuits, it has to be reduced by including power optimization techniques in the designs. Pulsed Latch is a popular technique of reducing power consumption which uses Pulsed Latches instead of flip-flops. As latches have lesser number of circuit elements compared to flip-flops, the area is also minimized. By implementing this pulsed latch technique, the linear feedback shift register can be designed with low power and area. The design entry is done in VHDL code and implemented using Cadence tool. In Cadence, Nclaunch, RTL Complier and Encounter tools are used for simulation, synthesis and implementation. With this method, the power reduction is achieved up to 41.99%

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Section: A Power Optimization Techniquesmentioning

confidence: 99%

Low Power Implementation of Linear Feedback Shift Registers

Jayasanthi¹,

AK²

2019

IJRTE

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“…Nowadays, every IC designer aims to reduce power consumption and decrease the size of electronics to reduce the cost of manufacturing. Each module of a digital system required appropriate design for the lowest possible power to keep pace with the scaling of technology, a single-chip integrated by billions of transistors using nano-scale CMOS processes [1] [2].…”

Section: Introductionmentioning

confidence: 99%

A 100 MHz 9.14-mW 8-Bit Shift Register Using Double-Edge Triggered Flip-Flop

Ekkurthi

Dasari

Akiri

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Double-edge triggered flip-flops (DETFF) project a solution to clock power reduction by lowering the clock frequency and maintains the same data rate. Hence, they are appropriate to be used as shift registers. This paper has reviewed several earlier designs of double-edge triggered flip-flops and presented an 8-bit low power shift register by using a newly designed DETFF. The major contribution of this work takes advantage of two parallel data paths that work in opposite phases of the single clock without an inverted input trigger. The proposed shift register design is realized using a typical 90-nm CMOS process. The post-layout results show that the proposed shift register reduces the power consumption by at least 17.2%.

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“…IC designers are facing the challenge of keeping low-power consumption thereof to extend the operation time. Each module of a digital system required appropriate design for the lowest possible power to keep the pace with the scaling of technology, e.g., a single chip integrated by billions of transistors using nano-scale CMOS processes [1] [2].…”

Section: Introductionmentioning

confidence: 99%

Low-Power High-Speed 8-Bit Shift Register Using Double-Edge Triggered Flip-Flops

2018

Proceedings of 2018 the 8th International Workshop on Computer Science and Engineering

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This investigation presents an 8-bit shift register based on a lower-power double-edge triggered (DETFF) flip-flop. The 8-bit shift register based on the low-power DETFF is carried out by using Cadence Virtuoso version 5.1 and TSMC 0.18 µm CMOS technology. The major contribution of the proposed design is a method using a double-clocking technique to latch data bits such that shorter time delay and the less power dissipation are achieved at the same time. The all-PVT-corner (process, voltage, temperature) postlayout simulation results demonstrates 34.970 mW at the highest 125 MHz clock rate.

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Design and analysis of linear feedback shift register(LFSR) using gate diffusion input(GDI) technique

Cited by 10 publications

References 9 publications

Low Power Implementation of Linear Feedback Shift Registers

Low Power Implementation of Linear Feedback Shift Registers

A 100 MHz 9.14-mW 8-Bit Shift Register Using Double-Edge Triggered Flip-Flop

Low-Power High-Speed 8-Bit Shift Register Using Double-Edge Triggered Flip-Flops

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