Design and Analysis of Low Power Dynamic Bus Based on RLC simulation

Abstract

In this paper, we propose a low power dynamic bus encoding scheme which simultaneously reduces the capacitive and inductive effects by the measurement of real RLC model. It should be noted that our method does not need a sufficient knowledge of the patterns on the bus. Our experimental results show that the proposed approach can save power consumption of the bus up to 12% compared to the nonencoded case. We also propose an area-aware scheme to optimize our circuits in terms of power consumption and area. The scheme can reduce the circuit area up to 29% while keeping almost the same power reduction.

Comparative Power Analysis of an Adaptive Bus Encoding Method on the MBUS Structure

“…where the supply voltage denoted as and the load capacitance denoted as are decided by the tape-out technology [3]. The maximum clock or operational frequency, denoted as , is the reciprocal of the sum of setup time ( setup), critical combinational path delay between flip flops ( propagation), clock to delay ( clk − ), and clock skew ( skew).…”