Design and Analysis of Low Power Memory Built in Self Test Architecture for SoC based Design

Vennelakanti, Sowmithra; Saravanan, S.

doi:10.17485/ijst/2015/v8i14/62716

Cited by 7 publications

(1 citation statement)

References 11 publications

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“…The author showed an improvement of 92.28% in power consumption compared to address generators using traditional LFSR. Another low-power MBIST is presented in [30]. It uses a combination of modulo-counter and gray code counter for address generation.…”

Section: Low Power Mbistmentioning

confidence: 99%

Testing nanometer memories: a review of architectures, applications, and challenges

Sontakke,

Atchina

2024

IJECE

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Newer defects in memories arising from shrinking manufacturing technologies demand improved memory testing methodologies. The percentage of memories on chips continues to rise. With shrinking technologies (10 nm up to 1.8 nm), the structure of memories is becoming denser. Due to the dense structure and significant portion of a chip, the nanometer memories are highly susceptible to defects. High-frequency specifications, the complexity of internal connections, and the process variation due to newer manufacturing technology further increased the probability of the physical failure of memories to a great extent. Memories need to be defect-free for the chip to operate successfully. Therefore, testing embedded memories has become crucial and is taking significant test costs. Researchers have proposed multiple approaches considering these factors to test the nanometer memories. They include using new fault models, march algorithms, memory built-in self-test (MBIST) architectures, and validation strategies. This paper surveys the methodologies presented in recent times. It discusses the core principles used in them, along with benefits. Finally, it discusses key opens in each and offers the scope for future research.

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Section: Low Power Mbistmentioning

confidence: 99%

Testing nanometer memories: a review of architectures, applications, and challenges

Sontakke,

Atchina

2024

IJECE

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Address Sequence Generator for Memory BIST

Shauchenka¹

2019

SSRG-IJCSE

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Design and Implimentation of Test Pattern Generator for Design Under Test

Ahmed¹,

Champa²

2016

IJRET

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The patterns generated by LFSR for BIST as lack of correlation between the test vectors. Hence in order to improve the correlation of the test vector the patterns were generated using gray counter and decoder. In this paper we implement low power BIST for 4-bit multiplier. Main aspect of this is to implement low power BIST with increased fault coverage. This use the gray counter, decoder and accumulator as test pattern generator with changing the seed value for every 2 power m cycle, so for this purpose which use counter for monitoring the number of cycles. Hence the respective area optimization and power reduction can be achieved. Simulation outcome on multiplier circuit show a limiting of area and power than reconfigurable Johnson counter and LFSR. We implement the design using verilog HDL and Tool used for implementation is XILINX 13.2 and simulation is performed by using modelsim.

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Design and Analysis of Low Power Memory Built in Self Test Architecture for SoC based Design

Cited by 7 publications

References 11 publications

Testing nanometer memories: a review of architectures, applications, and challenges

Testing nanometer memories: a review of architectures, applications, and challenges

Address Sequence Generator for Memory BIST

Design and Implimentation of Test Pattern Generator for Design Under Test

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