Design and Analysis of Multichannel LIGBTs in Junction Isolation Technology

Green, D.W.; Hardikar, S.; Tadikonda, R.; Sweet, M.; Vershinin, K.; Narayanan, E.M. Sankara

doi:10.1109/ted.2005.850627

Cited by 15 publications

(4 citation statements)

References 9 publications

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“…As highlighted, for Type 2 devices the substrate thickness must be reduced below 250 ptm before forward voltage drop enhancement can be achieved, for the current density considered here. Substrate Thickness (1tm) 3 Fig. 8 is the predicted forward voltage drop/clamped inductive switching (CIS) trade-off curve at 100 A/cm2 as a function of substrate thickness.…”

Section: Proposed Structurementioning

confidence: 99%

“…Furthermore, enhancement in terms of current density enables a reduction in the area consumed and therefore cost per unit. Previously it has been shown that the incorporation of additional MOS channels at the silicon surface, like in Multi-Channel LIGBTs [1] - [3], can enhance the current handling capabilities and forward voltage drop. However it must be ensured that the increase in current is not offset by the increase in silicon area consumed by the additional MOS cells.…”

Section: Introductionmentioning

confidence: 99%

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RESURFed Quasi Lateral IGBT Structure for High Current PICs

Narayanan

Tadikonda

Green

2007

Proceedings of the 19th International Symposium on Power Semiconductor Devices and IC's

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In this paper a new power device architecture is proposed. The concept is shown to significantly enhance the current carrying capability of devices suitable for integration in Power Integrated Circuits (PICs). The concept combines the advantages of the RESURF principle under blocking conditions to yield a compact device and uses multiple MOSFET cathode cells, formed on the backside of the wafer to yield a high level of vertical current modulation in the on-state. The new architecture is shown to significantly enhance the forward bias safe operating area and also the forward voltage drop by more than 50 %. Critically, it is also shown that the additional backside cathode cells have a minimal effect on the turn-off losses in comparison to a conventional lateral IGBT.

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Section: Proposed Structurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

RESURFed Quasi Lateral IGBT Structure for High Current PICs

Narayanan

Tadikonda

Green

2007

Proceedings of the 19th International Symposium on Power Semiconductor Devices and IC's

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“…Several techniques, floating BLN (N + buried layer) [2], buried hole diverter [3], P + collector connected to the outmost enclosing N + sinker [4], and an BLN layer is implanted into the EPI region [5] are used to alleviate the high substrate current. Multichannel LIGBTs (MC-LIGBT) have been previously demonstrated in the double epitaxial lower dielectric isolation [6]. The MC-LIGBT offers a reduction in forward voltage drop due to the additional channels, which drives the base of the PNP transistor in LIGBT.…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of a double RESURF 700V LIGBT with quasi-vertical DMOSFET in junction isolation technology

Tsai

Gong

Chan

et al. 2014

2014 IEEE 26th International Symposium on Power Semiconductor Devices &Amp; IC's (ISPSD)

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This paper presents the analysis of the substrate leakage current to anode current ratio of the 700V n-type lateral IGBT with quasi-vertical DMOSFET (QVDMOS) fabricated with junction isolation technology. To improve the substrate leakage, a p-type buried layer (BLP) is inserted between the ntype drift region and the n-type buried layer (BLN). A junction isolated p-region, which is connected to the BLP layer, is used to separate the N+ anode and the P+ anode. The measurement results show that this structure successfully eliminated the substrate current as well as to ensure high breakdown voltage. Furthermore, due to the use of the quasi-VDMOS cathode cell, additional current path enables a reduction in the forward voltage drop.

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“…This makes the vertical electric field under the anode be stronger than the transverse field, which causes a great amount of holes inject into the p-substrate when the device is turned on. Electrons are then attracted to the p-substrate to form the substrate current that will in turn to cause the malfunction of other on-chip low power devices [2]. According [3] to references, the ways to suppress the substrate current include to isolate LIGBT and the p-substrate by using SOI, though effective, the cost of the process increases at the same time; using double epilayers [4][5] [6] to isolate the substrate current; and using the MEMS [7] technique to suppress the substrate current.…”

Section: Introductionmentioning

confidence: 99%

The Study of Improving High Voltage LIGBT Substrate Leakage Current

Gong

2012

AMM

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This paper aims to the research of high voltage lateral insulated gate bipolar transistor (LIGBT) and proposes the design for reducing the substrate leakage current of this device. The junction between LIGBT’s p-type substrate and n-epi layer may have a large electrical field and causes the hole current to flow during the turn-on state. To prevent this substrate leakage current, an n-type buried layer (NBL) and a p-type buried layer (PBL) are used. The double reverse biased pn-junction structure effectively reduces the vertical electric field such that the substrate current is reduced by four orders of magnitude. The break down voltage of the LIGBT is not hurt by this added structure at all.

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Design and Analysis of Multichannel LIGBTs in Junction Isolation Technology

Cited by 15 publications

References 9 publications

RESURFed Quasi Lateral IGBT Structure for High Current PICs

RESURFed Quasi Lateral IGBT Structure for High Current PICs

Design and analysis of a double RESURF 700V LIGBT with quasi-vertical DMOSFET in junction isolation technology

The Study of Improving High Voltage LIGBT Substrate Leakage Current

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