Design and Analysis of Power Efficient TG Based Dual Edge Triggered Flip-Flops with Stacking Technique

Sabu, Neethu Anna; Batri, K.

doi:10.1142/s0218126620501236

Cited by 8 publications

(7 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…(%) DETFF TP t cq PDP LM1 [13] 36.18 31.68 16.19 LM2 [13] 2267.70 24.34 94.16 TCRFF [16] 26.48 39.59 55.71 LM C [15] 10.03 32.26 38.00 LG C [19] 21.99 41.80 54.72 IP C [19] 19.22 37.01 49.25 FN C [19] 4.68 34.15 37.41 EP1 [21] 51.05 4.88 53.56 EP2 [22] 66.58 5.36 64.89 SSPC [25] 7 3, the flip-flop proposed in this paper is superior to all the comparative DETFFs in terms of the total circuit power consumption, saving an average of 251.17% of the total power consumption. Moreover, it improved the average PDP by 44.32% and the delay by 9.71%.…”

Section: Experimental Results and Comparative Analysismentioning

confidence: 99%

Anti-interference low-power double-edge triggered flip-flop based on C-elements

Huang

Yang

Song

et al. 2022

Tsinghua Sci. Technol.

View full text Add to dashboard Cite

When the input signal has been interfered and glitches occur, the power consumption of Double-Edge Triggered Flip-Flops (DETFFs) will significantly increase. To effectively reduce the power consumption, this paper presents an anti-interference low-power DETFF based on C-elements. The improved C-element is used in this DETFF, which effectively blocks the glitches in the input signal, prevents redundant transitions inside the DETFF, and reduces the charge and discharge frequencies of the transistor. The C-element has also added pull-up and pull-down paths, reducing its latency. Compared with other existing DETFFs, the DETFF proposed in this paper only flips once on the clock edge, which greatly reduces the redundant transitions caused by glitches and effectively reduces power consumption. This paper uses HSPICE to simulate the proposed DETFF and other 10 DETFFs.The findings show that compared with the other 10 types of DETFFs, the proposed DETFF has achieved large performance indexes in the total power consumption, total power consumption with glitches, delays, and power delay product. A detailed analysis of variance indicates that the proposed DETFF features less sensitivity to process, voltage, temperature, and Negative Bias Temperature Instability (NBTI)-induced aging variations.

show abstract

Section: Experimental Results and Comparative Analysismentioning

confidence: 99%

Anti-interference low-power double-edge triggered flip-flop based on C-elements

Huang

Yang

Song

et al. 2022

Tsinghua Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…We have developed three 4-bit SRs named Transistor Count Reduction Technique SR (TCRSR), Series Stacking in TCR SR (S-TCRSR) and Forced Stacking of Transistor in TCR SR (FST in TCRSR) from three FFs named Transistor Count Reduction Technique Flip-Flop (TCRFF), Series Stacking in TCR Flip-Flop (S-TCRFF) and Forced Stacking of Transistor in TCRFF (FST in TCRFF) (Sabu and Batri, 2019). The first SR, TCRSR is made using a low-power transmission gate-based DFF.…”

Section: The Architecture Of Proposed Shift Registersmentioning

confidence: 99%

“…The second SR named S-TCRSR is derived from a series stacked FF called S-TCRFF (Sabu and Batri, 2019). It aims at the reduction of sub-threshold leakage current, one of the predominant factors of static power consumption (Narendra et al , 2001).…”

Section: The Architecture Of Proposed Shift Registersmentioning

confidence: 99%

“…The schematic arrangement of S-TCRSR and its simulation waveform are shown in Figures 5 and 6, respectively. The third SR (FST in TCRSR) is developed from a low-power forced stacking of transistors (FST) involved FF (Sabu and Batri, 2019). The technique is quite similar to the case of the dual threshold CMOS technique (DTCMOS), which involves the usage of transistors with multiple threshold voltages.…”

Section: The Architecture Of Proposed Shift Registersmentioning

confidence: 99%

“…This herding nature of elephant groups is applied in hydro-thermal power systems (Sambariya and Fagana, 2017), neural network systems (Sahlol et al , 2017), wireless sensor network systems (Correia et al , 2018), etc. This paper introduces three new designs of low-power and area-efficient SRs (TCRSR, S-TCRSR and FST in TCRSR) derived from three double-edge triggered D flip-flops (DETDFFs), namely, TCRFF, S-TCRFF and FST in TCRFF (Sabu and Batri, 2019). TCRFF has the least number of clocked MOS transistors, thereby reducing power consumption compared to the conventional FFs.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Power and area-efficient register designs involving EHO algorithm

Sabu

Batri

2020

Self Cite

View full text Add to dashboard Cite

Purpose This paper aims to design three low-power and area-efficient serial input parallel output (SIPO) register designs, namely, transistor count reduction technique shift register (TCRSR), series stacking in TCR shift register (S-TCRSR) and forced stacking of transistor in TCR shift register (FST in TCRSR). Shift registers (SR) are the basic building blocks of all types of digital applications. The performance of all the designs has been improved through one of the metaheuristic algorithms named elephant herding optimization (EHO) algorithm and hence suited for low-power very large scale integration (VLSI) applications. It is for the first time that the EHO algorithm is implemented in memory elements. Design/methodology/approach The registers together with clock network consume 18-36 percentage of the total power consumption of a microprocessor. The proposed designs are implemented using low-power and high-performance double edge-triggered D flip-flops with least count of clocked transistors involving transmission gate. The second and third register designs are developed from the modified version of the first one employing series and forced stacking, thereby reducing static power because of sub-threshold leakage current. The performance parameters such as power-delay-product (PDP) and leakage power are further optimized using the EHO algorithm. A greater reduction in power is achieved in all the designs by utilizing the EHO algorithm. Findings All the designs are simulated at a supply voltage of 1 V/500 MHz when the input switching activity is 25 percentage in Cadence Virtuoso using 45 nm CMOS technology. Nine recently proposed SR designs are simulated in the same conditions, and the performance has been compared with the proposed ones. The simulated results prove the excellence of proposed designs in different performance parameters like leakage power, energy-delay-product (EDP), PDP, layout area compared with the recent designs. The PDPdq value has a reduction of 95.9per cent (TCRSR), 96.6per cent (S-TCRSR) and 97per cent (FST in TCRSR) with that of a conventional shift register (TGSR). Originality/value The performance of proposed low-power SR designs is enhanced using EHO algorithm. The optimized performance results have been compared with a few optimization algorithms. It is for the first time that EHO algorithm is implemented in memory elements.

show abstract

Design Automation of Series Resonance Clocking in 14-nm FinFETs

Challagundla,

Bezzam,

Islam

2023

Circuits Syst Signal Process

View full text Add to dashboard Cite

Power-performance constraints have been the key driving force that motivated the microprocessor industry to bring unique design techniques in the past two decades. The rising demand for high-performance microprocessors increases the circuit complexity and data transfer rate, resulting in higher power consumption. This work proposes a set of energy recycling resonant pulsed flip-flops to reuse some of the dissipated energy using series inductor-capacitor (LC) resonance. Moreover, this work also presents wideband clocking architectures that use series LC resonance and an inductor tuning technique. By employing pulsed resonance, the switching power dissipated is recycled back. The inductor tuning technique aids in reducing the skew, increasing the robustness of the clock networks. This new resonant clocking architecture saves over 43% power and 90% reduced skew in clock tree networks and saves 44% power and 90% reduced skew in clock mesh networks, clocking a range of 1-5 GHz frequency, compared to conventional primary-secondary flip-flop-based clock networks. Implementation of resonant clock architectures on standard clock network benchmarks depicts 66% power Dhandeep Challagundla

show abstract

Design and Analysis of Power Efficient TG Based Dual Edge Triggered Flip-Flops with Stacking Technique

Cited by 8 publications

References 21 publications

Anti-interference low-power double-edge triggered flip-flop based on C-elements

Anti-interference low-power double-edge triggered flip-flop based on C-elements

Power and area-efficient register designs involving EHO algorithm

Design Automation of Series Resonance Clocking in 14-nm FinFETs

Contact Info

Product

Resources

About