2010 International Conference on Advances in Recent Technologies in Communication and Computing 2010
DOI: 10.1109/artcom.2010.20
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Design and Analysis of Robust Dual Threshold CMOS Full Adder Circuit in 32nm Technology

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Cited by 14 publications
(5 citation statements)
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“…The solution presented in this work is the use of a dual-threshold configuration [66,67] which provides a lower noise margin and higher voltage swing at the output compared to the diode-load and the dual-gate topology, respectively. Dual-threshold technology has been studied for several years and applied to the silicon technology, achieving power consumption reductions [68,69] and increasing the performance of the system in different aspects as delay [68,70], robust designs [71], asynchronous circuits [72], speed improvement [73] or glitch minimization [74]. The interdigitated and Corbino devices developed in this work present different electrical characteristics, such as V T .…”
Section: Unipolar Organic Dual-geometry Threshold Voltage Invertermentioning
confidence: 99%
“…The solution presented in this work is the use of a dual-threshold configuration [66,67] which provides a lower noise margin and higher voltage swing at the output compared to the diode-load and the dual-gate topology, respectively. Dual-threshold technology has been studied for several years and applied to the silicon technology, achieving power consumption reductions [68,69] and increasing the performance of the system in different aspects as delay [68,70], robust designs [71], asynchronous circuits [72], speed improvement [73] or glitch minimization [74]. The interdigitated and Corbino devices developed in this work present different electrical characteristics, such as V T .…”
Section: Unipolar Organic Dual-geometry Threshold Voltage Invertermentioning
confidence: 99%
“…The solution presented in this work is the use of a dual-threshold configuration [66,67] which provides a lower noise margin and higher voltage swing at the output compared to the diode-load and the dual-gate topology, respectively. Dual-threshold technology has been studied for several years and applied to the silicon technology, achieving power consumption reductions [68,69] and increasing the performance of the system in different aspects as delay [68,70], robust designs [71], asynchronous circuits [72], speed improvement [73] or glitch minimization [74]. The interdigitated and Corbino devices developed in this work present different electrical characteristics, such as V T .…”
Section: Unipolar Organic Dual-geometry Threshold Voltage Invertermentioning
confidence: 99%
“…Technology scaling, as stated by Moore where the transistor count in a chip should double at about every two years, is a significant factor in the ascendance of Integrated Circuits (ICs), providing higher transistor densities and voltage scaling due to the miniaturization of gate dimensions, internal capacitance, and resistance. Such improvements provided the IC designers with plenty of processing power per area unit of a chip and energy efficiency, making it the perfect combination for the usage of ICs in mobile applications [1].…”
Section: Introductionmentioning
confidence: 99%