Design and Analysis of Three-Stage Amplifier for Driving pF-to-nF Capacitive Load Based on Local Q-Factor Control and Cascode Miller Compensation Techniques

Cheng, Qi; Li, Weimin; Tang, Xian; Guo, Jianping

doi:10.3390/electronics8050572

Cited by 14 publications

(15 citation statements)

References 34 publications

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“…Thus, an RC feedback network (R F -C F ) models the feedback circuit. Loop-gain stability has been tested during the charge vs voltage conversion when R F -C F is bypassed [ 21 ]. The Opamp equivalent load capacitors are also taken into consideration by varying C F .…”

Section: Simulation Outcomes and Discussionmentioning

confidence: 99%

“…The stability, conditions are indicated by the phase margin (PM) and the gain-bandwidth product (GBP) within the Bode plot for the design of single-stage and two-stage amplifiers. However, the stability of multistage amplifiers requires advanced computations than single-or two-stage amplifiers; resulting from the existence of complex poles in high-order switch capabilities [ 6 , 20 , 21 ]. In addition, the desired performance requirements (GBP, PM) rely on the frequency compensation method and the value of the load capacitance C L1 .…”

Section: Introductionmentioning

confidence: 99%

“…In addition, the desired performance requirements (GBP, PM) rely on the frequency compensation method and the value of the load capacitance C L1 . For a complete validation of the front-end electronics with CMOS technology, the overall system specifications are needed [ 20 , 21 , 22 ]. In ref.…”

Section: Introductionmentioning

confidence: 99%

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An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

Jérôme

Evariste

Bernard

et al. 2021

Sensors

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The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consumption and higher readout bandwidth to match the low power requirement of its Short Strip application-specific integrated circuits (ASIC) (SSA) and to handle a large number of pileup events in the High-Luminosity Large Hadron Collider (LHC). A low-noise, wide bandwidth, and ultra-low power FEE for the pixel-strip sensor of the CMS has been designed and simulated in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process. The design comprises a Charge Sensitive Amplifier (CSA) and a fast Capacitor-Resistor-Resistor-Capacitor (CR-RC) pulse shaper (PS). A compact structure of the CSA circuit has been analyzed and designed for high throughput purposes. Analytical calculations were performed to achieve at least 998 MHz gain bandwidth, and then overcome pileup issue in the High-Luminosity LHC. The spice simulations prove that the circuit can achieve 88 dB dc-gain while exhibiting up to 1 GHz gain-bandwidth product (GBP). The stability of the design was guaranteed with an 82-degree phase margin while 214 ns optimal shaping time was extracted for low-power purposes. The robustness of the design against radiations was performed and the amplitude resolution of the proposed front-end was controlled at 1.87% FWHM (full width half maximum). The circuit has been designed to handle up to 280 fC input charge pulses with 2 pF maximum sensor capacitance. In good agreement with the analytical calculations, simulations outcomes were validated by post-layout simulations results, which provided a baseline gain of 546.56 mV/MeV and 920.66 mV/MeV, respectively, for the CSA and the shaping module while the ENC (Equivalent Noise Charge) of the device was controlled at 37.6 e− at 0 pF with a noise slope of 16.32 e−/pF. Moreover, the proposed circuit dissipates very low power which is only 8.72 µW from a 3.3 V supply and the compact layout occupied just 0.0205 mm2 die area.

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Section: Simulation Outcomes and Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

Jérôme

Evariste

Bernard

et al. 2021

Sensors

View full text Add to dashboard Cite

show abstract

“…The Q-factor cannot be, however, reduced easily since it is related to the stages' transconductances and output impedances that cannot be controlled easily. Local impedance attenuation (LIA) network along with auxiliary feedback loops are used in conjunction with cascode Miller compensation to reduce the high Q-factor using the cascode local impedance attenuation (CLIA) (Tan and Ki, 2015), the cascode global impedance attenuation (CGIA) (Aminzadeh et al, 2020), the cascode Miller compensation with local Q-factor control (CLQC) (Cheng et al, 2019) and the transconductance-enhancement cascode Miller compensation (TECMC) (Dong and Zhu, 2018).…”

Section: Introductionmentioning

confidence: 99%

Hybrid cascode compensation with Q-factor control module for three-stage OTAs driving ultra-large load capacitors

Aminzadeh

Valinezhad

2020

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Purpose The purpose of this study is to discuss the effect of hybrid cascode compensation with quality factor (Q-factor) control module for the three-stage amplifiers driving ultra-large load capacitors. Compared to the present frequency compensation solutions, it extends the amplifier bandwidth by establishing an extra AC feedback pathway besides the primary pathway through the Miller capacitor, increasing the loop gain at the gain–bandwidth product (GBW) frequency by pushing to the higher frequencies the nondominant poles. Design/methodology/approach A Q-factor control block is used to improve the damping factor of the compensation loop with no power or area overhead, thereby reducing the frequency peaking and the undesired oscillation in the time response for small load capacitors. The Q-factor control module is realized by a tiny-size on-chip capacitor, and provides an extra feedback loop to feed the damping current back to the input stage. A left-half-plane (LHP) zero is also introduced to further improve the stability. Findings A prototype of the proposed amplifier is simulated in 180-nm CMOS with a quiescent current of 24-µA from 1.80-V voltage supply. It achieves a 3.98-MHz gain–bandwidth product for 500-pF load capacitor, while the overall compensation capacitor is limited to 0.5-pF and the DC gain is extended beyond 100-dB. Originality/value The proposed amplifier is absolutely stable for the load capacitors ranging between 80-pF and 100-nF.

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“…As scaling continues, however, supply voltages also need to be scaled down to ensure device reliability. This results in reduced signal headroom and renders conventional cascode techniques unreliable [2,3]. For this reason, modern OTAs tend to involve a cascade of multiple stages (three or more) to achieve the desired gain.…”

Section: Introductionmentioning

confidence: 99%

Classification and Design Space Exploration of Low-Power Three-Stage Operational Transconductance Amplifier Architectures for Wide Load Ranges

2019

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Since operational transconductance amplifiers (OTAs) form the basic building blocks of many analog systems, the compensation of three-stage OTAs has attracted a lot of attention in the literature. Many different solutions to the stability problem of such OTAs have been proposed over the past 20 years, with each solution exhibiting different properties or targeting a different application. This work surveys a broad selection of previously reported architectures and proposes a novel classification scheme that exposes features common to seemingly different compensation architectures and serves as a guideline for which type of OTA is suitable for a given application. In addition, a novel figure of merit (FoM) is proposed to guide the designer in deciding which OTA architecture suits the tradeoffs specific to the application at hand. Theoretical discussions are further reinforced by transistor-level simulation results.

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Design and Analysis of Three-Stage Amplifier for Driving pF-to-nF Capacitive Load Based on Local Q-Factor Control and Cascode Miller Compensation Techniques

Cited by 14 publications

References 34 publications

An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

Hybrid cascode compensation with Q-factor control module for three-stage OTAs driving ultra-large load capacitors

Classification and Design Space Exploration of Low-Power Three-Stage Operational Transconductance Amplifier Architectures for Wide Load Ranges

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