Design and Applications for Embedded Networks-on-Chip on FPGAs

Abdelfattah, Mohamed S.; Bitar, Andrew; Betz, Vaughn

doi:10.1109/tc.2016.2621045

Cited by 16 publications

(11 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…An extensive increase in the size of the chip and the number of transistors per unit area allows developing chips with tens and hundreds of processor cores even now. At the same time, the problem of effective organization of a communication subsystem that would ensure quick data exchange between nodes of such NoCs is becoming urgent [2].…”

Section: Introductionmentioning

confidence: 99%

Development of routing algorithms in networks-on-chip based on two-dimensional optimal circulant topologies

Romanov

Lezhnev

Glukhikh

et al. 2020

Heliyon

View full text Add to dashboard Cite

This work is devoted to the study of application of new topologies in the design of networks-on-chip (NoCs). It is proposed to use two-dimensional optimal circulant topologies for NoC design, and it is developed an optimized routing algorithm with the decreased memory usage. The proposed routing algorithm was compared with Table routing, Clockwise routing, and Adaptive routing algorithms, previously developed for ring circulant topologies, and specialized routing algorithm for multiplicative circulants. The results of synthesis of routers implementing proposed routing algorithms are presented. The cost of ALM and register resources for the implementation of communication subsystems in NoCs with circulant topologies is estimated.

show abstract

Section: Introductionmentioning

confidence: 99%

Development of routing algorithms in networks-on-chip based on two-dimensional optimal circulant topologies

Romanov

Lezhnev

Glukhikh

et al. 2020

Heliyon

View full text Add to dashboard Cite

show abstract

“…Low‐power and energy‐efficient design is one of the main essential requirements of current and emerging NoC‐based systems but it trades‐off latency, throughput, and area 31‐35 . Like all integrated circuits, FPGAs dissipate static and dynamic power.…”

Section: Introductionmentioning

confidence: 99%

“…Low-power and energy-efficient design is one of the main essential requirements of current and emerging NoC-based systems but it trades-off latency, throughput, and area. [31][32][33][34][35] Like all integrated circuits, FPGAs dissipate static and dynamic power. Static power consumption is the power consumed by a device when it is not clocked and there is no circuit activity (all inputs are stable).…”

mentioning

confidence: 99%

A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip

Alaei

Yazdanpanah

2020

Concurrency and Computation

View full text Add to dashboard Cite

High performance system-on-chip (SoCs) designs have led to high-density integrated circuits using field programmable gate arrays (FPGAs) for rapid prototyping and reconfigurable digital circuits. Using FPGA reconfigurability, it is possible to design a configurable network-on-chip (NoC) for different applications. NoC architectures provide efficient communication infrastructures for implementing very large SoCs. In this article, we propose HiFMP, a high-performance FPGA-based multicrossbar prioritized NoC router. The aim followed by the proposed router is designing a low-power NoC router with high performance in terms of energy-efficiency, network throughput, area, and latency for efficient FPGA realization. HiFMP is a parameterizable router, and is effectively used for an FPGA-based NoC with mesh topology. Performance evaluations include network-level analysis and hardware exploration; the results demonstrate the effectiveness and high performance of HiFMP in terms of latency, throughput, power consumption, and area, comparing with the existing related architectures. K E Y W O R D S FPGA, low-power design, multicrossbar, network-on-chip, priority-based router 1 INTRODUCTION In high-density emerging SoC architectures, there are a large number of processing elements (PEs) communicating through intensive on-chip interconnections that significantly affect different aspects of the performance. For large SoCs, point-to-point and bus-based interconnections do not provide efficient on-chip network infrastructures because of large amount of hardware, high latency, high power consumption, and/or complicated synchronization. NoCs, as high-performance architectures, arise to overcome the limitations of traditional on-chip structures. 1-5 NoCs provide high-performance and power scalable and modular interconnections. In addition, with NoC architectures, the system complexity is reduced by separating communication and computation units. A NoC includes routers, links, and network interfaces in order to prepare a network infrastructure for interconnecting PEs. Links of NoCs consist of physical channels (i.e., a group of wires), and optional virtual channels (VCs) as a set of additional buffers in routers. 4-7 The channel bit-width (the number of wires in a unidirectional channel) depends on the bandwidth requirements of the applications and available chip area. Generally, links of NoC have two physical unidirectional channels for fully duplexed communication, allowing data to flow both ways without collisions. 1 Routers are the most important modules of the communication backbone of NoC architectures. So, it is essential to design them with low latency, low power consumption, and high throughput. The router complexity and performance impacts the latency, power consumption, area, throughput, and the cost of on-chip networks. 8 Field programmable gate arrays (FPGAs) are flexible, easy-to-use, and cost effective reprogrammable devices with fast and simple design flow. FPGA designers generally do not need to care for clock distribut...

show abstract

“…Development of elemental base of electronics and communication technologies opens up new opportunities and poses new challenges for their use to achieve new levels of computing system performance [ 1 , 2 , 3 ]. One of the fundamental problems in the field of Multiprocessor Systems-on-Chip (MPSoCs) [ 4 , 5 ] at present is the construction of communication structures and algorithms for exchanging data in Networks-on-Chip (NoCs) [ 6 ] of new generations. Development of communication tools allows combining a large number of processors into compact (dense) structures with a minimum diameter, minimum exchange delays, maximum bandwidth capability, reliability, and survivability with low hardware costs and power consumption within a single chip.…”

Section: Introductionmentioning

confidence: 99%

Routing in triple loop circulants: A case of networks-on-chip

Romanov

Starykh

2020

Heliyon

View full text Add to dashboard Cite

In this paper we propose and analyze various approaches to organizing routing in a triple loop circulant topologies as applied to networks-on-chip: static routing based on universal graph search algorithms, such as Dijkstra's algorithm and a possible implementation using Table routing; algorithms created analytically based on an engineering approach with taking into account the structural features of triple loop circulant graphs (Advanced clockwise, Direction selection); an algorithm created on the basis of a mathematical analysis of graph structure and solving the problem of enumerating coefficients at generators (Coefficients finding algorithm). Efficiency, maximum graph paths, occupied memory resources, and calculation time of the algorithms developed are estimated. Comparison of various variants of the algorithms is made and recommendations on their application for the development of networks-on-chip with triple loop circulant topologies are given. It is shown that Advanced clockwise and Direction selection algorithms guarantee that the packet reaches the destination node, but often in more steps than the shortest path. Nevertheless, they themselves are simpler and require less hardware resources than other algorithms. In turn, Coefficients finding algorithm has great computational complexity, but is optimal and, in comparison with Dijkstra's algorithm, is much simpler for RTL implementation which reduces network-on-chip routers resources cost.

show abstract

Design and Applications for Embedded Networks-on-Chip on FPGAs

Cited by 16 publications

References 15 publications

Development of routing algorithms in networks-on-chip based on two-dimensional optimal circulant topologies

Development of routing algorithms in networks-on-chip based on two-dimensional optimal circulant topologies

A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip

Routing in triple loop circulants: A case of networks-on-chip

Contact Info

Product

Resources

About