Design and characterization of a 10bit pipeline- ADC for 100MSps in 0.18&amp;#x03BC;m CMOS

Gamauf, Christoph; Nemecek, A.; Leisenberger, Friedrich Peter; Promitzer, G.

doi:10.1109/austrochip.2014.6946311

Cited by 4 publications

(2 citation statements)

References 7 publications

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“…A 50 Ω-impedance driver has not been implemented due to power consumption reasons. Together with the active integration stage an integrated dual-slope analog-todigital converter (ADC) [3] with 10 bit and 250 kSps is realized. Therefore, an integrated comparator triggers a dedicated digital counter if the integration limits are reached.…”

Section: Functional Blocksmentioning

confidence: 99%

Universal Integrated Photodetector Platform

2018

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Within this work we developed a universal integrated photodetector platform for the detection, amplification and digitalization of various optical data signals. The concept features two internal plus two external photodiodes, signal amplification and output stages each. For each application a combination of the optimal input detector, the suitable amplifier plus gain setting and the appropriate output stage can be combined individually.

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Section: Functional Blocksmentioning

confidence: 99%

Universal Integrated Photodetector Platform

2018

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“…The implementation of high-speed ADC as a bulding block of readout ASICs in CMOS processes of technology nodes 130-180 nm results in high power consumption and large chip area. For known ADCs working with sampling rate more than 100 MHz the power consumption still reaches tens of mW [1][2][3][4] despite of the application of new architectural solutions [5]. That is inappropriate application for a low-power design of multichannel read-out ASICs.…”

Section: Introductionmentioning

confidence: 99%

Implementation of the interpolator for signal peak detection in read-out ASIC

Shumikhin¹,

Azarov²,

Bulbakov³

et al. 2020

J. Inst.

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A: A prototype interpolator for signal peak detection in read-out ASIC is presented. It uses interpolation algorithm for finding additional points between ADC samples. This allows to increase an accuracy for signal peak detection. Behavioral models of interpolator for Spline and Lagrange algorithm were realized and compared. Interpolator was designed in 180 nm UMC MMRF CMOS process. It is based on a 6th order Lagrange interpolation polynomial. The interpolator ensures the accuracy of signal peak finding is less than 1.5 LSB of ADC at sampling frequency of 25 MHz and 200 ns peaking time of 2nd order shaper.

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Design and implementation of high speed pipeline a/d converter for image processing and communication based applications

Basavarajappa,

Rather

2024

Computing, Networks, and Renewable Energy

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Design and characterization of a 10bit pipeline- ADC for 100MSps in 0.18μm CMOS

Cited by 4 publications

References 7 publications

Universal Integrated Photodetector Platform

Universal Integrated Photodetector Platform

Implementation of the interpolator for signal peak detection in read-out ASIC

Design and implementation of high speed pipeline a/d converter for image processing and communication based applications

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