Design and characterization of parallel prefix adders using FPGAs

Hoe, David H. K.; Martinez, Chris D.; Vundavalli, Sri Jyothsna

doi:10.1109/ssst.2011.5753800

Cited by 28 publications

(14 citation statements)

References 8 publications

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“…As such, the methods discussed in this paper illustrate techniques for implementing fault tolerance on a critical component that could be applied to other systems on an FPGA. This paper expands upon our work previously reported in conference papers regarding the characterization of arithmetic logic on FPGAs [2] and the implementation of fault tolerant adder designs on FPGAs [3]. In particular, this paper examines the implementation of fault tolerance in adders that utilize a parallel-prefix scheme for rapid computation of the carry signals.…”

Section: Introductionmentioning

confidence: 70%

“…Additional test circuitry was synthesized on the FPGA to allow generation of the appropriate test signals. Our test methodology for removing delays due to cabling and the added test logic was previously reported in [2]. An example of the resulting waveforms obtained from our logic analyzer for measuring the delay is given in Figure 17.…”

Section: Resultsmentioning

confidence: 99%

“…This section reviews the performance of various adder topologies implemented on FPGAs [2]. This information bears relevance for understanding the fault tolerant architectures discussed in the next section.…”

Section: Basic Adder Design and Performance On Fpgasmentioning

confidence: 99%

“…The measurement methodology is described in detail in [2]. Of note is the fact that the linear RCA adder is faster than all the other adders at a bit width of 128 or less, as summarized on the graph in Figure 5.…”

Section: Basic Adder Design and Performance On Fpgasmentioning

confidence: 99%

“…Of note is the fact that the linear RCA adder is faster than all the other adders at a bit width of 128 or less, as summarized on the graph in Figure 5. Analysis and simulation results for the Spartan 3E FPGA adders indicated for 256 bit widths that the parallel-prefix adders become faster than the linear RCAs [2].…”

Section: Basic Adder Design and Performance On Fpgasmentioning

confidence: 99%

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FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders

2013

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This paper examines fault tolerant adder designs implemented on FPGAs which are inspired by the methods of modular redundancy, roving, and gradual degradation. A parallel-prefix adder based upon the Kogge-Stone configuration is compared with the simple ripple carry adder (RCA) design. The Kogge-Stone design utilizes a sparse carry tree complemented by several smaller RCAs. Additional RCAs are inserted into the design to allow fault tolerance to be achieved using the established methods of roving and gradual degradation. A triple modular redundant ripple carry adder (TMR-RCA) is used as a point of reference. Simulation and experimental measurements on a Xilinx Spartan 3E FPGA platform are carried out. The TMR-RCA is found to have the best delay performance and most efficient resource utilization for an FPGA fault-tolerant implementation due to the simplicity of the approach and the use of the fast-carry chain. However, the superior performance of the carry-tree adder over an RCA in a VLSI implementation makes this proposed approach attractive for ASIC designs.

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Section: Introductionmentioning

confidence: 70%

Section: Resultsmentioning

confidence: 99%

Section: Basic Adder Design and Performance On Fpgasmentioning

confidence: 99%

Section: Basic Adder Design and Performance On Fpgasmentioning

confidence: 99%

Section: Basic Adder Design and Performance On Fpgasmentioning

confidence: 99%

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