Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications

Sreenivasulu, V. Bharath; Narendar, Vadthiya

doi:10.1149/2162-8777/abddd4

Cited by 30 publications

(4 citation statements)

References 45 publications

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“…The hybrid spacer shows higher I ON compared to Air spacer due to the presence of Si 3 N 4 in fin extension which enhances carrier densities. 30 An increment of 1.14Â in I ON has been noticed from Air to HfO 2 spacer. Moreover, the increment of I ON by high-k spacer is due to an increase in carrier densities.…”

Section: Simulation Results and Discussionmentioning

confidence: 92%

Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Sreenivasulu

Narendar

2021

Int J RF Mic Comp-Aid Eng

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Multi-fin devices are the most reliable option for terahertz (THz) frequency applications at nano-regime. In this work impact of spacer engineering on multi-fin SOI FET performance is evaluated by invoking single low-k (Air), high-k (Si 3 N 4 , HfO 2 ), and hybrid dual-k (Air + Si 3 N 4 ) spacer in the underlap section at nano-regime. The simulation study reveals that the high-k (HfO 2 ) spacer gives a higher switching ratio (I ON /I OFF ) in the order of ~10 7 , subthreshold swing (SS) = 72 mV/dec, drain induced barrier lowering (DIBL) = 22.14 mV/V and quality factor (Q) = g m /SS = 0.16 μS-dec/mV. Furthermore, to measure the suitability of the device for high frequency applications various analog/RF parameters are studied. The high-k (HfO 2 ) spacer dominates DC and analog performance, whereas the low-k (Air) spacer dominates the RF domain with f T = 1.26 THz, GBW = 0.251 THz, TFP = 29 THz range, and with smaller intrinsic delays. Hybrid dual-k spacer (Air + Si 3 N 4 ) outperforms in terms of gain (A V ) and output resistance (R o ). The Air spacer exhibits lower dynamic power of 2.09 aJ/μm and power consumption of 1.04 aJ/μm. The linearity metrics for multi-fin SOI FET parameters like g m2 , g m3 , HD1, HD2, THD, and VIP2 are also studied. The Air spacer followed by hybrid spacer outperforms in linearity, and harmonic distortion components and ensures its potential for RF applications at nano-regime.

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Section: Simulation Results and Discussionmentioning

confidence: 92%

Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Sreenivasulu

Narendar

2021

Int J RF Mic Comp-Aid Eng

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“…The three-dimensional (3D) device structure of the NS-FET is based on 10 nm technology node [11]- [14]. Fig.…”

Section: Device Structures and Simulation Methodsmentioning

confidence: 99%

“…This inhibits the gate current from evading into the channel and ensures insulator sealing. The device functions more efficiently when a dielectric material is placed in between the channel's source and drain [11].…”

Section: Device Structures and Simulation Methodsmentioning

confidence: 99%

Spacer Dielectric Analysis of Multi-Channel Nanosheet FET for Nanoscale Applications

Panigrahy,

Amudalapalli,

Rani

et al. 2024

IEEE Access

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This work investigates the effect of single and dual-k spacer materials consisting of different dielectric constants (k) in optimized nano-channel gate-stack nanosheet (NS-FET) employing hafnium oxide and silicon dioxide as gate insulator to improve its sub-threshold performance. The effect of the external lowk spacer modification in the dual-k spacer has been shown by adjusting the inner high-k spacer. The draininduced barrier lowering (DIBL) in this modification with dual-k spacer is 14 mV/V, which is a significant improvement above single spacer NS-FET. The Visual TCAD 3D Cogenda tool is used to examine the performance of the developed NS-FET with air, single, dual-k, and hybrid spacers. The CADENCE platform is used to perform circuit aspects. Additionally, a comparison of the device architecture's performance study with respect to DC characteristics is made. DC parameters of the proposed device are established: ION to IOFF ratio of approximately 10 5 , DIBL of approximately 14 mV/V, sub-threshold swing (SS) of approximately 62 mV/dec, and low threshold voltage (Vth) of 0.38 V. The analysis on power consumption for advanced NS-FET is also analyzed with single-k and dual-k spacers. The performance of single-k and dual-k spacer dielectric variation for CMOS inverter is also shown. Furthermore, low power consumption by this NS-FET ensures improved device performance suitable for nanoscale semiconductor industries.

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“…Over the past decade, the scaling of nanofeatures has progressed to the sub-10 nm scale, primarily driven by the microelectronics industry’s quest for continual enhancements in device performance. − The drive toward sub-10 nm features is important for maintaining the trajectory of device miniaturization, which is essential for improving performance, power efficiency, and packing density in integrated circuits . Nevertheless, sub-10 nm resolutions are still challenging, as current high-resolution top-down techniques like electron beam and extreme ultraviolet lithography are hampered by cost and efficiency issues. − Overcoming these hurdles requires innovative solutions, which has led to interest in bottom-up methods like block copolymer (BCP) lithography .…”

Section: Introductionmentioning

confidence: 99%

Controlled Anisotropic Wetting by Plasma Treatment for Directed Self-Assembly of High-χ Block Copolymers

Putranto,

Petit-Etienne,

Cavalaglio

et al. 2024

ACS Appl. Mater. Interfaces

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The directed self-assembly (DSA) of block copolymers (BCPs) is a promising next-generation lithography technique for high-resolution patterning. However, achieving lithographically applicable BCP organization such as out-of-plane lamellae requires proper tuning of interfacial energies between the BCP domains and the substrate, which remains difficult to address effectively and efficiently with high-χ BCPs. Here, we present the successful generation of anisotropic wetting by plasma treatment on patterned spin-on-carbon (SOC) substrates and its application to the DSA of a high-χ Si-containing material, poly(1,1-dimethylsilacyclobutane)-block-polystyrene (PDMSB-b-PS), with a 9 nm half pitch. Exposing the SOC substrate to different plasma chemistries promotes the vertical alignment of the PDMSB-b-PS lamellae within the trenches. In particular, a patterned substrate treated with HBr/O 2 plasma gives both a neutral wetting at the bottom interface and a strong PS-affine wetting at the sidewalls of the SOC trenches to efficiently guide the vertical BCP lamellae. Furthermore, prolonged exposure to HBr/O 2 plasma enables an adjustment of the trench width and an increased density of BCP lines on the substrate. Experimental observations are in agreement with a free energy configurational model developed to describe the system. These advances, which could be easily implemented in industry, could contribute to the wider adoption of self-assembly techniques in microelectronics, and beyond to applications such as metasurfaces, surface-enhanced Raman spectroscopy, and sensing technologies.

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Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications

Cited by 30 publications

References 45 publications

Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Spacer Dielectric Analysis of Multi-Channel Nanosheet FET for Nanoscale Applications

Controlled Anisotropic Wetting by Plasma Treatment for Directed Self-Assembly of High-χ Block Copolymers

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